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III. Multicore Processors (6): 

III. Multicore Processors (6) Dezső Sima Spring 2007 (Ver. 2.0)  Dezső Sima, 2007

Slide2: 

10.4.1 Gemini 10.4.2 UltraSPARC IV line 10.4.3 UltraSPARC T line 10.4. Sun’s MC processors

10.4 Evolution of Sun’s processor lines: 

Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf Figure: Overview of Sun’s major processor families Multi-core processors 10.4 Evolution of Sun’s processor lines

Slide4: 

Gemini (cancelled) 130 nm 4/2004 10.4.1 Gemini 10.4 Sun’s MC processors

10.4.1 Gemini (1): 

Figure: The Gemini processor JBus contr. Mem. contr. Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf 10.4.1 Gemini (1)

10.4.1 Gemini (2): 

Figure: Block diagram and die shot of the Gemini Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf 10.4.1 Gemini (2)

10.4.1 Gemini (3): 

Figure: Main features of the Gemini processor Source: Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf 10.4.1 Gemini (3)

10.4.1 Gemini (4): 

10.4.1 Gemini (4) Table: Main features of Sun’s Gemini

Slide9: 

UltraSPARC IV Jaguar 3/2004 130 nm 10.4.2 UltraSPARC IV line 10.4 Sun’s MC processors UltraSPARC IV+ Panther 9/2005 90 nm

10.4.2 UltraSPARC IV (1): 

Figure : UltraSPARC IV (Jaguar) Source: C. Boussard: Architecture des processeurshttp://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf ARB: Arbiter 10.4.2 UltraSPARC IV (1)

10.4.2 UltraSPARC IV (2): 

Source: Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf Figure: Floor plan of the UltraSPARC IV 10.4.2 UltraSPARC IV (2)

10.4.2 UltraSPARC IV (3): 

10.4.2 UltraSPARC IV (3) Table: Main features of Sun’s UltraSPARC IV processor

10.4.2 UltraSPARC IV+ (1): 

Figure: UltraSPARC IV+ (Panther) Source: C. Boussard: Architecture des processeurs,http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf 10.4.2 UltraSPARC IV+ (1)

10.4.2 UltraSPARC IV+ (2): 

Source: Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf Figure: Die shot and floor plan of the UltraSPARCIV+ 19.7 x 17.0 mm 10.4.2 UltraSPARC IV+ (2) UltraSPARC IV+

10.4.2 UltraSPARC IV+ (3): 

Sources: Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf Figure: Contrasting the floor plans of the UltraSPARC IV and UltraSPARC IV+ dies UltraSPARC IV UltraSPARC IV+ 130 nm/356 mm2/66 mtrs 90 nm/335 mm2/295 mtrs 10.4.2 UltraSPARC IV+ (3)

10.4.2 UltraSPARC IV+ (4): 

Figure: Schmoo plot of the UltraSPARCIV+ Source: Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf 10.4.2 UltraSPARC IV+ (4)

10.4.2 UltraSPARC IV+ (5): 

10.4.2 UltraSPARC IV+ (5) Table: Main features of Sun’s IV+ processor

Slide18: 

10.4.3 UltraSPARC T line 10.4 Sun’s MC processors UltraSPARC T1 Niagara 11/2005 90 nm UltraSPARC T2 Niagara 2 2007 65 nm

10.4.3 UltraSPARC T1 (1): 

Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf Figure: Block diagram of the UltraSPARC T1 (Niagara) 10.4.3 UltraSPARC T1 (1)

10.4.3 UltraSPARC T1 (2): 

Figure: Pipeline stages of the Niagara cores (scalar FX cores) Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf 10.4.3 UltraSPARC T1 (2)

10.4.3 UltraSPARC T1 (3): 

Figure: Die shot of Niagara Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf 10.4.3 UltraSPARC T1 (3)

10.4.3 UltraSPARC T1 (4): 

Figure: Floor plan and main features of Niagara Source: Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf 10.4.3 UltraSPARC T1 (4)

10.4.3 UltraSPARC T1 (5): 

10.4.3 UltraSPARC T1 (5) Table: Main features of Sun’s UltraSPARC T1 processor

10.4.3 UltraSPARC T2 (1): 

Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Figure: Block diagram of UltraSPARC 2 (Niagara-2) 10.4.3 UltraSPARC T2 (1)

10.4.3 UltraSPARC T2 (2): 

Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Figure: block diagram of the cores in Niagara 2 10.4.3 UltraSPARC T2 (2)

10.4.3 UltraSPARC T2 (3): 

Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Figure: The full crossbar swith of Niagara 2 10.4.3 UltraSPARC T2 (3)

10.4.3 UltraSPARC T2 (4): 

Source: Golla R, „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Main features and floor plan of the Niagara-2 10.4.3 UltraSPARC T2 (4)

10.4.3 UltraSPARC T2 (5): 

Source: Grohoski G., „Niagara-2,” Aug. 2006, http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_master.pdf Figure: Floor plan of the Niagara-2 10.4.3 UltraSPARC T2 (5)

10.4.3 UltraSPARC T2 (6): 

Source: Kanter D.” Niagara II, The Hydra Returns,” http://realworldtech.com/page.cfm?ArticleID=RWT090406012516&p=4 Figure: Comparison of the block diagrams of Niagara-1 and -2 10.4.3 UltraSPARC T2 (6)

10.4.3 UltraSPARC T2 (7): 

10.4.3 UltraSPARC T2 (7) Table: Main features of Sun’s UltraSPARC T2 processor

10.4 Literature (1): 

10.4 Literature (1) UltraSPARC IV Kapil S., „Gemini,” 2003, http://www.hotchips.org/archives/hc15/3_Tue/12.sun.pdf Boussard C., „Architecture des processeurs,”,http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf Krewell K., „UltraSPARCIV Mirrors Predecessor, MPR, Nov. 10, 2003, http://www.sun.com/processors/feature/M45_UltraSPARC4_rpnt.pdf Dixit A. et al., „Implementation and Productization of a 4th Generation 1.8 GHz Dual-Core SPARC V9 Microprocessor, Febr. 2006, http://www.ewh.ieee.org/r6/scv/ssc/Feb2006.pdf Gemini UltraSPARC IV+ Boussard C., „Architecture des processeurs,” http://laser.igh.cnrs.fr/IMG/pdf/SUN-CNRS-archi-cpu-3.pdf - „UltraSPARC IV+ Processor User’s Manual Supplement,” Ver. 1.0, Sun Microsystems, Oct. 2005, http://www.sun.com/processors/manuals/USIVplus_v1.0.pdf - „UltraSPARC IV Processor User’s Manual Supplement,” Ver. 1.0, Sun Microsystems, Apr. 2004, http://www.sun.com/processors/manuals/USIV_v1.0.pdf - UltraSPARC IV Processor Architecture Overview, Technical Whitepaper, Febr. 2004, http://www.sun.com/processors/whitepapers/us4_whitepaper.pdf

Slide32: 

UltraSPARC T1 UltraSPARC T2 Laudon J., „UltraSPARC T1: A 32-threaded CMP for Servers, 2006, http://www.cs.duke.edu/courses/fall06/cps220/lectures/UltraSparc_T1_Niagra.pdf Golla R., „Niagara2: A Highly Threaded Server-on-a-Chip,” Oct. 2006, http://www.opensparc.net/pubs/preszo//06/04-Sun-Golla.pdf Grohoski G., „Niagara-2,” Aug. 2006, http://www.opensparc.net/pubs/preszo/06/HotChips06_09_ppt_master.pdf Kanter D.” Niagara II, The Hydra Returns,” http://realworldtech.com/page.cfm?ArticleID=RWT090406012516&p=4 10.4 Literature (2) McGhan H., „Niagara 2 Opens The Floodgates,” Microprocessor Report, Nov. 6, 2006, pp. 1-9 Kongetira P., Aingaran K., Olukoton K., „Niagara: A 32-way Multithreaded SPARC Processor,” IEEE Micro, March-April 2005, pp. 21-29 - „UltraSPARC T1 Supplement to the UltraSPARC architecture 2005, Draft D2.0, March 2006, http://opensparc-t1.sunsource.net/specs/UST1-UASuppl-current-draft-P-EXT.pdf

Slide33: 

SPARC64 VI SPARC64 VII 10.5. Fujitsu’s MC processors

Slide34: 

SPARC64 VI Olympus 90 nm 2007 SPARC64 VII Jupiter 65 nm 2008 Dual-core SPARC64 line 10.5 Fujitsu’s MC processors

10.5 SPARC64 VI: 

Reservation Stations (E: FX, F: FP, A: Adress, FP/SP: L/S) Execution Units (EX: FX, FL: PA, AGEN: Adr. Gen.) Source:Inouo A., „Fujitsu SPARC64 VI, Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf 10.5 SPARC64 VI Figure: Block diagram of the SPARC64 VI

10.5 SPARC64 VII (1): 

Source:Inouo A., „Fujitsu SPARC64 VI, Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf 10.5 SPARC64 VII (1) Figure: Block diagram of the SPARC64 VII

10.5 SPARC64 VI/VII (2): 

10.5 SPARC64 VI/VII (2) Table: Main features of Fujitiu’s multi-core processors (superscalar RISC’s)

10.5 Literature: 

10.5 Literature Sparc64 line Inouo A., „Fujitsu SPARC64 VI,” Fall Microprocessor Forum, Oct. 2006, Fujitsu Ltd., http://www.ssken.gr.jp/lib/nl/2006/sci/2/3_inouePPT_pre.pdf Krewell K., „SPARC’s Still Going Strong,” Microprocessor Report, Nov. 14, 2005, pp. 1-3 Krewell K., „Fujitsu Makes SPARC See Double,” Microprocessor Report, Nov. 24, 2003, pp. 1-3 Maruyama T., „SPARC64 VI/VI+ Next Generation processor,” MPF, Oct. 2005, http://primeserver.fujitsu.com/primepower/event/report/pf-2005/pdf/mpf2005scr.pdf

Slide39: 

PA-8800 PA-8900 10.6. HP’s MC processors

Slide40: 

PA-8800 Mako 130 nm 2/2004 PA-8900 Shortfin 130 nm 5/2005 Dual-core PA-8xxx processors (PA 8700-based) 10.6 HP’s dual-core processors

10.6 PA-8800 (1): 

Source: E&M Computing, http://www.emet.co.il/events/amd/processors.pdf Figure: The underlaying PA-8700 core 10.6 PA-8800 (1)

10.6 PA-8800 (2): 

Sources: Lostcircuits, Oct. 2001, http://www.lostcircuits.com/cpu/hp_pa8800/3dblock4.jpg Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf Figure: Block diagram of the PA-8800 10.6 PA-8800 (2)

10.6 PA-8800 (3): 

Figure: Floorplan of the Mako Source: Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf 10.6 PA-8800 (3)

10.6 PA-8800 (4): 

Figure: Contrasting the Floorplans of the PA-8700 and PA-8800 processors Sources: E&M Computing, http://www.emet.co.il/events/amd/processors.pdf Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf 10.6 PA-8800 (4)

10.6 PA-8900 (1): 

10.6 PA-8900 (1) Table: Main features of HP’s PA-8800 and PA-8900 processors

10.6 Literature: 

10.6 Literature MS, „HP PA-8800 RISCProcessor,” Lostcircuits, Oct. 2001, http://www.lostcircuits.com/cpu/hp_pa8800/2.shtml PA 8800/8900 Johnson D., „HP’s Mako processor”, Oct. 2001, ftp.parisc-linux.org/docs/whitepapers/mako_mpf_2001.pdf Weissmann P., „The OpenPA Project,” First Edition, Berlin, 2007, http://www.openpa.net/openpa-print_1-0.pdf

Slide47: 

XLR line (embedded) 10.7. RMI’ MC processors

Slide48: 

XLR 90 nm 5/2005 XLR line (embedded) 10.7 RMI’s MC processors

10.7 XLR line (1): 

Cores: 64-bit MIPS64 with XLR enhancements 4-way multithreaded up to 1.5 Gz 32KB L1 I$, 32 KB L1 D$ branch prediction Figure: XLR cores Aim: Embedded systems, such as processing cores from packet data transfers, cryptography functions, authentication operations, TCP/IP CRC calculations and network interface data management. Source: http://www.razamicroelectronics.com/documents/XLR_PO_20050512_Product_Overview.pdf 10.7 XLR line (1)

10.7 XLR line (2): 

http://www.razamicroelectronics.com/documents/XLR_Family_2001PB_Product_Brief.pdf Figure: Architecture of the XLR family 10.7 XLR line (2)

10.7 XLR line (3): 

Source: Krewell K., „A New MIPS Powerhouse Arrives,”, Microprocessor Report, 5/17/2005 http://www.razamicroelectronics.com/chinese/press/MP_Report_XLR.pdf Figure: Block diagram of RMI’s XLR family 10.7 XLR line (3)

10.7 XLR line (4): 

Figure: The Fast Messaging Network (FMN) Source: http://www.razamicroelectronics.com/documents/XLR_PO_20050512_Product_Overview.pdf 10.7 XLR line (4)

10.7 XLR line (5): 

Source: Krewell K., „A New MIPS Powerhouse Arrives,”, Microprocessor Report, 5/17/2005 http://www.razamicroelectronics.com/chinese/press/MP_Report_XLR.pdf Figure: The Memory Distributed Interconnect (MDI) (providing 484 Gbits/s bandwidth) 10.7 XLR line (5)

10.7 XLR line (6): 

Source: Krewell K., „A New MIPS Powerhouse Arrives,”, Microprocessor Report, 5/17/2005 http://www.razamicroelectronics.com/chinese/press/MP_Report_XLR.pdf Figure: Floor plan of the XLR die 10.7 XLR line (6)

10.7 XLR line (7): 

10.7 XLR line (7) Table: Main features of RMI’s XLR lines

10.7 Literature: 

10.7 Literature XLR series - „XLR Processor Product Overview,” Preliminary, May 2005, http://www.razamicroelectronics.com/documents/XLR_PO_20050512_Product_Overview.pdf Krewell K., „A New MIPS Powerhouse Arrives,”, Microprocessor Report, 5/17/2005 http://www.razamicroelectronics.com/chinese/press/MP_Report_XLR.pdf - Multicore, multithreaded chips ship with Linux,” LinuxDevices, May 2005, http://linuxdevices.com/news/NS8376430165.html - „RMI XLR Processor Family Product Brief,” Document # 2001PB, RMI Inc., 2007, http://www.razamicroelectronics.com/documents/XLR_Family_2001PB_Product_Brief.pdf