REGISTER & COUNTER

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Registers and Counters:

9/3/2012 331_18 1 Registers and Counters Register & Counters Sandesh dubey Electrical and Computer Engineering

Registers:

9/3/2012 331_18 2 Registers Flip-flops (and latches) packaged in sets Quad register => 4 D flip-flops with common clock CLR_BAR => async, active-0, clear signal Common register types Multi-port Shift Universal

Quad Register:

9/3/2012 331_18 3 Quad Register D Q C CLR A D Q C CLR B D Q C CLR C D Q C CLR D CLK CLR_BAR Q A Q B Q C Q D D A D B D C D D

Quad 2-Port Register:

9/3/2012 331_18 4 Quad 2-Port Register D Q C CLR A D Q C CLR B D Q C CLR C D Q C CLR D CLK CLR_BAR Q A Q B Q C Q D SEL A 1 B 1 C 1 D 1 A 0 B 0 C 0 D 0 I 1 I 0 I 1 I 0 I 1 I 0 I 1 I 0

Shift Registers:

9/3/2012 331_18 5 Shift Registers Type Serial input / Serial output Serial input / Parallel output Parallel input / Serial output Parallel input / Parallel output Direction Left shift Right shift Universal

Serial Input / Serial Output:

9/3/2012 331_18 6 Serial Input / Serial Output D Q C CLR A D Q C CLR B D Q C CLR C D Q C CLR D CLK CLR_BAR D A Q D

Serial Input / Parallel Output:

9/3/2012 331_18 7 Serial Input / Parallel Output D Q C CLR A D Q C CLR B D Q C CLR C D Q C CLR D CLK CLR_BAR D A Q A Q B Q C Q D

Universal Shift Register:

9/3/2012 331_18 8 Universal Shift Register OP 1 OP 0 Mode 0 0 Hold 0 1 Shift Left 1 0 Shift Right 1 1 Parallel Load D A D B D C D D Q A Q B Q C Q D OP 0 OP 1 SR SL CLK CLR_BAR

Universal Shift Register:

9/3/2012 331_18 9 Universal Shift Register D Q C CLR A D Q C CLR B D Q C CLR C D Q C CLR D CLK CLR_BAR Q A Q B Q C Q D OP 1 OP 0 I 3 I 2 I 1 I 0 I 3 I 2 I 1 I 0 I 3 I 2 I 1 I 0 I 3 I 2 I 1 I 0 D A D B D C D D SL SR

Counters:

9/3/2012 331_18 10 Counters Characteristic Description Modulus Length of sequence Coding Count sequence Direction Up or down Resetable Reset to zero Loadable Load a specific value

Example 4-bit Counters:

9/3/2012 331_18 11 Example 4-bit Counters 4-bit Binary / Hex / Mod-16 Counter 0000, 0001, 0010, … 1110, 1111, 0000, 0001, … 4-bit BCD / Decade / Mod-10 Counter 0000, 0001, 0010, … 1000, 1001, 0000, 0001, … 4-bit Ring Counter 1000, 0100, 0010, 0001, 1000, 0100, …

Changing Counting Modulus:

9/3/2012 331_18 12 Changing Counting Modulus D A D B D C D D Q A Q B Q C Q D RCO EN CLK CLR LD 4-bit Binary Counter Note: Synchronous Load and Clear … 1000, 1001, 0000, 0001, …

Ring Counter:

9/3/2012 331_18 13 Ring Counter … 1000, 0100, 0010, 0001, 1000, 0100 … Q B Q A CLK 2-bit Binary Counter O 0 I 1 I 0 2-to-4 Decoder O 1 O 2 O 3

Ring Counter:

9/3/2012 331_18 14 Ring Counter CK 1 0 Q B 1 0 Q A 1 0 O 0 1 0 O 1 1 0 O 2 1 0 O 3 1 0

Shift Register Ring Counter:

9/3/2012 331_18 15 Shift Register Ring Counter D A D B D C D D Q A Q B Q C Q D SR CK SL Universal Shift Register OP 1 OP 0 … 1000, 0100, 0010, 0001, 1000, 0100 … CLK 1 0 0 0 1 1 0 0 /

Self-Correcting Ring Counter:

9/3/2012 331_18 16 Self-Correcting Ring Counter D A D B D C D D Q A Q B Q C Q D SR CK SL Universal Shift Register OP 1 OP 0 … 1000, 0100, 0010, 0001, 1000, 0100 … CLK 1 0 0 0 1 1 0 0 /

Synchronous Moore Machine:

9/3/2012 331_18 17 Synchronous Moore Machine Present State Input Comb Ckt Memory Comb Ckt Output Is Only a Function of Present State Output Clock Next State

Synchronous Mealy Machine:

9/3/2012 331_18 18 Synchronous Mealy Machine Output Is Function of Present State AND Present Input Present State Input Comb Ckt Memory Comb Ckt Output Clock Next State

Sequential PLDs:

9/3/2012 331_18 19 Sequential PLDs

Sequential PLDs:

9/3/2012 331_18 20 Sequential PLDs Combinational Circuit Memory Clk Input Next State Present State Comb Ckt Output

Programmable Macrocells:

9/3/2012 331_18 21 Programmable Macrocells Configurations Registered output active-0 logic state Registered output active-1 logic state Combinational output active-0 logic state Combinational output active-1 logic state Primary input Present state input

Summary:

9/3/2012 331_18 22 Summary Registers Counters Sequential PLDs

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