lec12

Lecture 12Advanced Combinational ATPG Algorithms: 

Lecture 12 Advanced Combinational ATPG Algorithms FAN – Multiple Backtrace (1983) TOPS – Dominators (1987) SOCRATES – Learning (1988) Legal Assignments (1990) EST – Search space learning (1991) BDD Test generation (1991) Implication Graphs and Transitive Closure (1988 - 97) Recursive Learning (1995) Test Generation Systems Test Compaction Summary

FAN -- Fujiwara and Shimono(1983): 

FAN -- Fujiwara and Shimono (1983) New concepts: Immediate assignment of uniquely-determined signals Unique sensitization Stop Backtrace at head lines Multiple Backtrace

PODEM Fails to Determine Unique Signals: 

PODEM Fails to Determine Unique Signals Backtracing operation fails to set all 3 inputs of gate L to 1 Causes unnecessary search

FAN -- Early Determination of Unique Signals: 

FAN -- Early Determination of Unique Signals Determine all unique signals implied by current decisions immediately Avoids unnecessary search

PODEM Makes Unwise Signal Assignments: 

PODEM Makes Unwise Signal Assignments Blocks fault propagation due to assignment J = 0

Unique Sensitization of FAN with No Search: 

Unique Sensitization of FAN with No Search FAN immediately sets necessary signals to propagate fault Path over which fault is uniquely sensitized

Headlines: 

Headlines Headlines H and J separate circuit into 3 parts, for which test generation can be done independently

Contrasting Decision Trees: 

Contrasting Decision Trees PODEM decision tree FAN decision tree

Multiple Backtrace: 

PODEM – Depth-first search 6 times Multiple Backtrace FAN – breadth-first passes – 1 time PODEM – depth-first passes – 6 times

AND Gate Vote Propagation: 

AND Gate Vote Propagation AND Gate Easiest-to-control Input – # 0’s = OUTPUT # 0’s # 1’s = OUTPUT # 1’s All other inputs -- # 0’s = 0 # 1’s = OUTPUT # 1’s [5, 3] [5, 3] [0, 3] [0, 3] [0, 3]

Multiple Backtrace Fanout Stem Voting: 

Multiple Backtrace Fanout Stem Voting Fanout Stem -- # 0’s = S Branch # 0’s, # 1’s = S Branch # 1’s [5, 1] [1, 1] [3, 2] [4, 1] [5, 1] [18, 6]

Multiple Backtrace Algorithm: 

Multiple Backtrace Algorithm repeat remove entry (s, vs) from current_objectives; If (s is head_objective) add (s, vs) to head_objectives; else if (s not fanout stem and not PI) vote on gate s inputs; if (gate s input I is fanout branch) vote on stem driving I; add stem driving I to stem_objectives; else add I to current_objectives;

Rest of Multiple Backtrace: 

Rest of Multiple Backtrace if (stem_objectives not empty) (k, n0 (k), n1 (k)) = highest level stem from stem_objectives; if (n0 (k) > n1 (k)) vk = 0; else vk = 1; if ((n0 (k) != 0) && (n1 (k) != 0) && (k not in fault cone)) return (k, vk); add (k, vk) to current_objectives; return (multiple_backtrace (current_objectives)); remove one objective (k, vk) from head_objectives; return (k, vk);

TOPS – DominatorsKirkland and Mercer (1987): 

TOPS – Dominators Kirkland and Mercer (1987) Dominator of g – all paths from g to PO must pass through the dominator Absolute -- k dominates B Relative – dominates only paths to a given PO If dominator of fault becomes 0 or 1, backtrack

SOCRATES Learning (1988): 

SOCRATES Learning (1988) Static and dynamic learning: a = 1 f = 1 means that we learn f = 0 a = 0 by applying the Boolean contrapositive theorem Set each signal first to 0, and then to 1 Discover implications Learning criterion: remember f = vf only if: f = vf requires all inputs of f to be non-controlling A forward implication contributed to f = vf

Improved Unique Sensitization Procedure: 

Improved Unique Sensitization Procedure When a is only D-frontier signal, find dominators of a and set their inputs unreachable from a to 1 Find dominators of single D-frontier signal a and make common input signals non-controlling

Constructive Dilemma: 

Constructive Dilemma [(a = 0) (i = 0)] [(a = 1) (i = 0)] (i = 0) If both assignments 0 and 1 to a make i = 0, then i = 0 is implied independently of a

Modus Tollens and Dynamic Dominators: 

Modus Tollens and Dynamic Dominators Modus Tollens: (f = 1) [(a = 0) (f = 0)] (a = 1) Dynamic dominators: Compute dominators and dynamically learned implications after each decision step Too computationally expensive

EST – Dynamic Programming (Giraldi & Bushnell): 

EST – Dynamic Programming (Giraldi & Bushnell) E-frontier – partial circuit functional decomposition Equivalent to a node in a BDD Cut-set between circuit part with known labels and part with X signal labels EST learns E-frontiers during ATPG and stores them in a hash table Dynamic programming – when new decomposition generated from implications of a variable assignment, looks it up in the hash table Avoids repeating a search already conducted Terminates search when decomposition matches: Earlier one that lead to a test (retrieves stored test) Earlier one that lead to a backtrack Accelerated SOCRATES nearly 5.6 times

Fault B sa1: 

Fault B sa1

Fault h sa1: 

Fault h sa1

Implication Graph ATPGChakradhar et al. (1990): 

Implication Graph ATPG Chakradhar et al. (1990) Model logic behavior using implication graphs Nodes for each literal and its complement Arc from literal a to literal b means that if a = 1 then b must also be 1 Extended to find implications by using a graph transitive closure algorithm – finds paths of edges Made much better decisions than earlier ATPG search algorithms Uses a topological graph sort to determine order of setting circuit variables during ATPG

Example and Implication Graph: 

Example and Implication Graph

Graph Transitive Closure: 

Graph Transitive Closure When d set to 0, add edge from d to d, which means that if d is 1, there is conflict Can deduce that (a = 1) F When d set to 1, add edge from d to d

Consequence of F = 1: 

Consequence of F = 1 Boolean false function F (inputs d and e) has deF For F = 1, add edge F F so deF reduces to d e To cause de = 0 we add edges: e d and d e Now, we find a path in the graph b b So b cannot be 0, or there is a conflict Therefore, b = 1 is a consequence of F = 1

Related Contributions: 

Related Contributions Larrabee – NEMESIS -- Test generation using satisfiability and implication graphs Chakradhar, Bushnell, and Agrawal – NNATPG – ATPG using neural networks & implication graphs Chakradhar, Agrawal, and Rothweiler – TRAN --Transitive Closure test generation algorithm Cooper and Bushnell – Switch-level ATPG Agrawal, Bushnell, and Lin – Redundancy identification using transitive closure Stephan et al. – TEGUS – satisfiability ATPG Henftling et al. and Tafertshofer et al. – ANDing node in implication graphs for efficient solution

Recursive LearningKunz and Pradhan (1992): 

Recursive Learning Kunz and Pradhan (1992) Applied SOCRATES type learning recursively Maximum recursion depth rmax determines what is learned about circuit Time complexity exponential in rmax Memory grows linearly with rmax

Recursive_Learning Algorithm: 

Recursive_Learning Algorithm for each unjustified line for each input: justification assign controlling value; make implications and set up new list of unjustified lines; if (consistent) Recursive_Learning (); if (> 0 signals f with same value V for all consistent justifications) learn f = V; make implications for all learned values; if (all justifications inconsistent) learn current value assignments as consistent;

Recursive Learning: 

Recursive Learning i1 = 0 and j = 1 unjustifiable – enter learning i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 g2 g1 h1 i2

Justify i1 = 0: 

Justify i1 = 0 Choose first of 2 possible assignments g1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 g2 g1 = 0 h1 i2

Implies e1 = 0 and f1 = 0: 

Implies e1 = 0 and f1 = 0 Given that g1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Justify a1 = 0, 1st Possibility: 

Justify a1 = 0, 1st Possibility Given that g1 = 0, one of two possibilities i1 = 0 j = 1 a1 = 0 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies a2 = 0: 

Implies a2 = 0 Given that g1 = 0 and a1 = 0 i1 = 0 j = 1 a1 = 0 b1 h c1 k d1 b a d c d2 c2 b2 a2 = 0 f2 e2 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies e2 = 0: 

Implies e2 = 0 Given that g1 = 0 and a1 = 0 i1 = 0 j = 1 a1 = 0 b1 h c1 k d1 b a d c d2 c2 b2 a2 = 0 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Now Try b1 = 0, 2nd Option : 

Now Try b1 = 0, 2nd Option Given that g1 = 0 i1 = 0 j = 1 a1 b1 = 0 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies b2 = 0 and e2 = 0: 

Implies b2 = 0 and e2 = 0 Given that g1 = 0 and b1 = 0 i1 = 0 j = 1 a1 b1 = 0 h c1 k d1 b a d c d2 c2 b2 = 0 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Both Cases Give e2 = 0, So Learn That: 

Both Cases Give e2 = 0, So Learn That i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Justify f1 = 0: 

Justify f1 = 0 Try c1 = 0, one of two possible assignments i1 = 0 j = 1 a1 b1 h c1 = 0 k d1 b a d c d2 c2 b2 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies c2 = 0: 

Implies c2 = 0 Given that c1 = 0, one of two possibilities i1 = 0 j = 1 a1 b1 h c1 = 0 k d1 b a d c d2 c2 = 0 b2 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies f2 = 0: 

Implies f2 = 0 Given that c1 = 0 and g1 = 0 i1 = 0 j = 1 a1 b1 h c1 = 0 k d1 b a d c d2 c2 = 0 b2 a2 f2 = 0 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Try d1 = 0: 

Try d1 = 0 Try d1 = 0, second of two possibilities i1 = 0 j = 1 a1 b1 h c1 k d1 = 0 b a d c d2 c2 b2 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies d2 = 0: 

Implies d2 = 0 Given that d1 = 0 and g1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 = 0 b a d c d2 = 0 c2 b2 a2 f2 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Implies f2 = 0: 

Implies f2 = 0 Given that d1 = 0 and g1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 = 0 b a d c d2 = 0 c2 b2 a2 f2 = 0 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 = 0 e1 = 0

Since f2 = 0 In Either Case, Learn f2 = 0: 

Since f2 = 0 In Either Case, Learn f2 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 = 0 e2 = 0 h2 g2 h1 i2 g1 = 0 f1 e1

Implies g2 = 0: 

Implies g2 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 = 0 e2 = 0 h2 g2 = 0 h1 i2 g1 = 0 f1 e1

Implies i2 = 0 and k = 1: 

Implies i2 = 0 and k = 1 i1 = 0 j = 1 a1 b1 h c1 k = 1 d1 b a d c d2 c2 b2 a2 f2 = 0 e2 = 0 h2 g2 = 0 h1 i2 = 0 g1 = 0 f1 e1

Justify h1 = 0: 

Justify h1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 g2 g1 h1 = 0 i2 Second of two possibilities to make i1 = 0

Implies h2 = 0: 

Implies h2 = 0 Given that h1 = 0 i1 = 0 j = 1 a1 b1 h c1 k d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 = 0 g2 g1 h1 = 0 i2

Implies i2 = 0 and k = 1: 

Implies i2 = 0 and k = 1 Given 2nd of 2 possible assignments h1 = 0 i1 = 0 j = 1 a1 b1 h c1 k = 1 d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 = 0 g2 g1 h1 = 0 i2 = 0

Both Cases Cause k = 1 (Given j = 1), i2 = 0: 

Both Cases Cause k = 1 (Given j = 1), i2 = 0 Therefore, learn both independently i1 = 0 j = 1 a1 b1 h c1 k = 1 d1 b a d c d2 c2 b2 a2 f2 e2 f1 e1 h2 g2 g1 h1 i2 = 0

Other ATPG Algorithms: 

Other ATPG Algorithms Legal assignment ATPG (Rajski and Cox) Maintains power-set of possible assignments on each node {0, 1, D, D, X} BDD-based algorithms Catapult (Gaede, Mercer, Butler, Ross) Tsunami (Stanion and Bhattacharya) – maintains BDD fragment along fault propagation path and incrementally extends it Unable to do highly reconverging circuits (parallel multipliers) because BDD essentially becomes infinite

Fault Coverage and Efficiency: 

Fault Coverage and Efficiency Fault coverage = Fault efficiency # of detected faults Total # faults # of detected faults Total # faults -- # undetectable faults =

Test Generation Systems: 

Test Generation Systems SOCRATES With fault simulator

Test Compaction: 

Test Compaction Fault simulate test patterns in reverse order of generation ATPG patterns go first Randomly-generated patterns go last (because they may have less coverage) When coverage reaches 100%, drop remaining patterns (which are the useless random ones) Significantly shortens test sequence – economic cost reduction

Static and Dynamic Compaction of Sequences: 

Static and Dynamic Compaction of Sequences Static compaction ATPG should leave unassigned inputs as X Two patterns compatible – if no conflicting values for any PI Combine two tests ta and tb into one test tab = ta tb using D-intersection Detects union of faults detected by ta & tb Dynamic compaction Process every partially-done ATPG vector immediately Assign 0 or 1 to PIs to test additional faults

Compaction Example: 

Compaction Example t1 = 0 1 X t2 = 0 X 1 t3 = 0 X 0 t4 = X 0 1 Combine t1 and t3, then t2 and t4 Obtain: t13 = 0 1 0 t24 = 0 0 1 Test Length shortened from 4 to 2

Summary: 

Summary Test Bridging, Stuck-at, Delay, & Transistor Faults Must handle non-Boolean tri-state devices, buses, & bidirectional devices (pass transistors) Hierarchical ATPG -- 9 Times speedup (Min) Handles adders, comparators, MUXes Compute propagation D-cubes Propagate and justify fault effects with these Use internal logic description for internal faults Results of 40 years research – mature – methods: Path sensitization Simulation-based Boolean satisfiability and neural networks