lec22

Lecture 22Delta IDDQ Testing and Built-In Current Testing: 

Lecture 22 Delta IDDQ Testing and Built-In Current Testing Current limit setting Testing time issues Delta IDDQ testing (D IDDQ) Built-in current testing sensors Summary

Current Limit Setting: 

Current Limit Setting Should try to get it < 1 mA Histogram for 32 bit microprocessor

Hewlett-Packard / Sandia Laboratories Results: 

Hewlett-Packard / Sandia Laboratories Results HP – static CMOS standard cell, 8577 gates, 436 FF Sandia Laboratories – 5000 static RAM tests Reject rate for various tests:

Failure Distribution in Hewlett-Packard Chip: 

Failure Distribution in Hewlett-Packard Chip

% Functional Failures After 100 Hours Life Test: 

% Functional Failures After 100 Hours Life Test Work of McEuen at Ford Microelectronics

Lower / Upper IDDQ Test Time Limits – McEuen (Ford): 

Lower / Upper IDDQ Test Time Limits – McEuen (Ford)

Delta IDDQ Testing -- Thibeault: 

Delta IDDQ Testing -- Thibeault Use derivative of IDDQ at test vector as current signature D IDDQ (i) = IDDQ (i) – IDDQ (i – 1) Leads to a narrower histogram Eliminates variation between chips and between wafers P – probability of false test decisions

IDDQ Versus DIDDQ: 

IDDQ Versus DIDDQ

Difference in Histograms: 

Difference in Histograms A – test escapes, B – yield loss

Parameters for Estimating P: 

Parameters for Estimating P Ddef -- minimum | DIDDQ | peak from active defect, mg = good mean, mb = bad mean

Example Differential IDDQ Histogram: 

Example Differential IDDQ Histogram Better peak resolution with | D IDDQ (i) |, doubles point count

DIDDQ Testing Results: 

DIDDQ Testing Results

IDDQ Built-in Current Testing – Maly and Nigh: 

IDDQ Built-in Current Testing – Maly and Nigh Build current sensor into ground bus of device-under-test Voltage drop device & comparator Compares virtual ground VGND with Vref at end of each clock – VGND > Vref only in bad circuits Activates circuit breaker when bad device found

Conceptual BIC Sensor: 

Conceptual BIC Sensor

CMOS BIC Sensor: 

CMOS BIC Sensor

Setting Optimal # Transistors in Block: 

Setting Optimal # Transistors in Block Must partition chip into functional units, each with its own BIC Too large a unit – combined leakage currents erroneously trigger BIC sensor Idefmin – smallest defect current Inoisemax – maximum noise-related peak supply current Minimum area sensor design at Idefmin and IDDQ intersection Nmax – maximum # transistors in 1 BIC unit

Graph for Choosing Nmax: 

Graph for Choosing Nmax

Summary: 

Summary IDDQ current limit setting to differentiate between good and bad circuits is difficult IDDQ testing is becoming more problematic Greater leakage currents in MOSFETs in deep sub-micron technologies Harder to discriminate elevated IDDQ from 100,000 transistor leakage currents DIDDQ holds promise to alleviate problems Built-in current testing holds promise