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The Design of aHigh-BandwidthSigma-Delta Modulator: 

The Design of a High-Bandwidth Sigma-Delta Modulator Brian Limketkai and Bret Victor

Project Motivation and Goals: 

Project Motivation and Goals High demand for high data rate wireless devices IEEE standard for wireless LAN: 802.11a ADC specs: Nyquist rate of 20 MS/s Resolution of 7 to 10 bits Low power Can we use a Sigma-Delta converter? Robust against circuit imperfections Not traditionally used in high-bandwidth applications

Sigma-Delta Specs: 

Sigma-Delta Specs Dynamic Range: > 62 dB (10 bits) Ideal maximum SNR for modulator of order L and oversampling ratio OSR: OSR chosen to be 16: fs = 320 MHz L chosen to be 4 Predicts ideal dynamic range of 80 dB

Cascade vs Single-Loop: 

Cascade vs Single-Loop Matching Single-loops very robust against circuit imperfections Cascades use digital filters for error cancellation, so better circuits required Stability Cascades guaranteed to be stable Single-loops difficult to stabilize SNR degradation, especially at low OSR

2-1-1 Cascade Topology: 

2-1-1 Cascade Topology 1 d3 1 d2 1 d1 1 c3 1 c2 1 c1 1 b3 1 b2 1 b1 2 a4 1 a3 1 a2 1 a1 Zero-Order Hold Scope1 Scope 4 Scope 3 Scope 1 Quantizer 3 Quantizer 2 Quantizer 1 out4 Output 3 out3 Output 2 out2 Output 1 Limit 4 Limit 3 Limit 2 Limit 1 az -1 1-bz -1 Integrator 4 az -1 1-bz -1 Integrator 3 az -1 1-bz -1 Integrator 2 az -1 1-bz -1 Integrator 1 Input Signal Experimental Dither 3 Experimental Dither 2

Scaling: 

Scaling 2 d3 2 d2 1 d1 1 c3 1 c2 1 c1 1 b3 1/2 b2 2 b1 1/2 a4 1/2 a3 1/2 a2 1/2 a1 Zero-Order Hold Scope1 Scope 4 Scope 3 Scope 1 Quantizer 3 Quantizer 2 Quantizer 1 out4 Output 3 out3 Output 2 out2 Output 1 Limit 4 Limit 3 Limit 2 Limit 1 az -1 1-bz -1 Integrator 4 az -1 1-bz -1 Integrator 3 az -1 1-bz -1 Integrator 2 az -1 1-bz -1 Integrator 1 Input Signal Experimental Dither 3 Experimental Dither 2 a1 = a2 a4 = 2 a1 a3

Final Scaling: 

Final Scaling 2 d3 2 d2 1 d1 1/2 c3 1/2 c2 1 c1 1/2 b3 1/4 b2 1 b1 1/2 a4 1/2 a3 1/2 a2 1/2 a1 Zero-Order Hold Scope1 Scope 4 Scope 3 Scope 1 Quantizer 3 Quantizer 2 Quantizer 1 out4 Output 3 out3 Output 2 out2 Output 1 Limit 4 Limit 3 Limit 2 Limit 1 az -1 1-bz -1 Integrator 4 az -1 1-bz -1 Integrator 3 az -1 1-bz -1 Integrator 2 az -1 1-bz -1 Integrator 1 Input Signal Experimental Dither 3 Experimental Dither 2

Noise: 

Noise Thermal Noise M is oversampling ratio Quantization Noise  is the converter LSB Quantization noise limited for OSR < 16 OSR noise power (dB) C = 100 fF C = 200 fF C = 500 fF C = 1 pF thermal noise quantization noise

Modeling Analog Components: 

Modeling Analog Components Settling time Settling accuracy Single-Sampling-Cap Integrator vin vfb vout Cs Cp Ci 1 1 2 2

Amplifier Specifications: 

Amplifier Specifications Not too difficult Converter power 40 mW

Noise Shaping in Simulink Model: 

Noise Shaping in Simulink Model 0 0.01 0.02 0.03 0.04 0.05 0.06 -180 -160 -140 -120 -100 -80 -60 signal bandwidth 2nd order 3rd order 4th order output power (dBFS) frequency / fs

Noise Shaping in Spectre Model: 

Noise Shaping in Spectre Model 0 0.01 0.02 0.03 0.04 0.05 0.06 -180 -160 -140 -120 -100 -80 -60 output power (dBFS) frequency / fs signal bandwidth 2nd order 3rd order 4th order

SNR vs Input Power: 

SNR vs Input Power -80 -70 -60 -50 -40 -30 -20 -10 0 -10 0 10 20 30 40 50 60 70 SNR (dB) input power (dBFS) 65 dB dynamic range

Conclusions: 

Conclusions Use of Sigma-Deltas feasible for wireless systems Limited by quantization noise, not thermal noise Circuit specifications are not too tough