project17 presentation

ELECTRONIC BATTLE TANK GAMEVHDL Programming on FPGAWith VGA and PS/2 Interfaces: 

ELECTRONIC BATTLE TANK GAME VHDL Programming on FPGA With VGA and PS/2 Interfaces ECE 445 Senior Design Team 17 December 1, 2005 Seung O, Sungmin Kim, Sangwoo Park

Objective: 

Objective The purpose of this project is to simulate a Battle Tank board game using VHDL codes, FPGA, VGA monitor and joy pad. The playing boards will be on the computer screen and the inputs from a user come from a joy pad.

Game Overview : 

Game Overview Designed for two players Each player has its own tank on each side of corners Each tank is loaded with bombs and fires them to hit the other player’s tank The trajectory of a bomb is always parabolic

Game Overview: 

Game Overview Each player has a chance per turn to move its tank’s position and fire a bomb A tank can move in four directions on the screen Each tank can only move its position before it launches a bomb. A player can choose the force of the bomb before shooting

Game Overview: 

Game Overview Shooting a bomb will finish one’s turn and shifts it to the other. Six times of hits will eventually lead to death. A player who kills the other’s tank first is the winner of the game.

Block Diagram: 

Block Diagram

Block Diagram of Main Controller: 

Block Diagram of Main Controller Main Controller Tank1 Tank2 Joy pad Controller Data Enable Enable Enable Response Response Start

Block Diagram of Tank entity: 

Block Diagram of Tank entity TANK BOMB VGA Sync POWER Enable Enable Enable Response Response Response

Component Description: 

Component Description ‘Tank’ entity implements tank object involves Bomb and Power as subcomponents. initiates Bomb’s operation and receives feedback whether or not it hit the opponent. reports its hit state to the Power entity and gets feedback from it whether power has left. Once it gets a signal from Bomb that the opponent has been hit, it sends out the signal notifying the other tank. it also receives a signal that it’s been hit by the opponent and sends out the signal to the power subcomponent. If it receives a signal of power outage, it displays crashing flashes onto the VGA screen.

Component Description: 

Component Description ‘Bomb’ entity subcomponent within a Tank entity implements a bomb that flies from an initiating tank to the opponent tank. ignited by a signal from a tank, and makes a parabolic movement additionally determined by the Force input until it either hits the opponent tank or falls onto the ground. As soon as it stops movement by either of the above mentioned causes it sends out a response signal to the super entity.

Component Description: 

Component Description ‘Power’ entity another subcomponent in a Tank entity displays power status of the super entity. Once it receives a signal from a tank, it decrements the power by one sixth of the total, displaying with a colored bar. If the power reaches one before outage, (i.e. one sixth is left), it warns the Tank entity by sending Warning signal.

VHDL testing and Simulation: 

VHDL testing and Simulation Simulated using ModelSim XE II Checked RTL schematics for correctness Xilinx ISE used for checking synthesis, Map and Place & Route reports Tested each of components separately and integrated them in the end

Design Statistics: 

Design Statistics Design Statistics Design Summary -------------- Number of errors: 0 Number of warnings: 14 Logic Utilization: Total Number Slice Registers: 333 out of 3,840 8% Number used as Flip Flops: 274 Number used as Latches: 59 Number of 4 input LUTs: 1,240 out of 3,840 32% Logic Distribution: Number of occupied Slices: 891 out of 1,920 46% Number of Slices containing only related logic: 891 out of 891 100% Number of Slices containing unrelated logic: 0 out of 891 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 1,632 out of 3,840 42% Number used as logic: 1,240 Number used as a route-thru: 392 Number of bonded IOBs: 30 out of 173 17% IOB Flip Flops: 2 IOB Latches: 1 Number of GCLKs: 8 out of 8 100% Total equivalent gate count for design: 14,499 Additional JTAG gate count for IOBs: 1,440 Peak Memory Usage: 121 MB Maximum Frequency Timing Summary: --------------- Speed Grade: -5 Minimum period: 9.489ns (Maximum Frequency: 105.391MHz) Minimum input arrival time before clock: 8.143ns Maximum output required time after clock: 24.505ns Maximum combinational path delay: 14.775ns

Key Assignments: 

Key Assignments

Scan CodesBelow is the scan code table used for the joy pad implementation.: 

Scan Codes Below is the scan code table used for the joy pad implementation.

Features of Hardware: 

Features of Hardware Two controllers compatible with VGA input/output and joy-pad adapter 15-pin D-type Connectors for the controllers PS/2 interface

Controller: 

Controller

Controller: 

Controller Configuration Controller wiring Tests Problems

Configuration: 

Configuration

Keyboard Module: 

Keyboard Module

Controller Wiring: 

Controller Wiring

Tests: 

Tests Holding a button or buttons for more than 10 seconds (OK) Pressing two or more buttons simultaneously (OK) Pressing buttons very fast at random (once, a program down)

Problems: 

Problems Tedious Soldering Excessive heat from soldering ruined the module Finding the best combination for the configuration