VHDL Tutorial (Complete)

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Complete about VHDL

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VHDL What is VHDL and what is its connection with brain building? VHDL stands for V(ery High Speed Integrated Circuit) Hardware Description Language. Before we can answer why VHDL is thought to be highly relevant to the field of brain building, we first need to have some idea of what VHDL is.

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An HDL is a high level language (similar to C, Pascal, Fortran, etc) used to specify the design of electronic circuits. With modern programmable hardware (i.e. configuring bit strings can be sent into a programmable chip to tell the chip how to wire itself up (i.e. to configure itself). Modern hardware compilers can take a high level description of an electronic circuit (e.g. written in an HDL such as VHDL , or Verilog , or ABEL , etc), and translate it into configuring bit strings , which are then used to configure a programmble chip (e.g. Xilinx’s Virtex chip). Thanks to Moore’s Law, the number of programmable logic gates (e.g. AND gates, NAND gates, etc) in today’s chips are now in the millions. With such electronic capacities on a single chip, it is now possible to place whole electronic systems on a chip .

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This has advantages and disadvantages. The advantage is that Electronics become more sophisticated and powerful and cheaper. The disadvantage is that electronics becomes harder to design. Earlier versions of HDLs operated more at the gate level of description (e.g. “connect the output of gate A to the input of gate B”). But, as chips increased in their logic gate count, the above rather low level of description became increasingly impractical due to the huge number of gates on a single chip. To cope with this problem, HDLs are taking an ever more behavioral level of description. Electronic designers nowadays give a behavioral or functional description of what they want their circuit to perform, and the HDL compiler does the rest.

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e.g. instead of saying “connect this gate to that gate”, one says “multiply these two numbers and store the result in this buffer”. The HDL compiler then translates the latter statement into the Corresponding circuitry that performs the required function. Nowadays, it is almost as easy to program hardware as to program software ! This is not strictly true, since to be able to use an HDL well, one needs to understand the principles of digital electronic design (e.g. multiplexors, flip-flops, buffers, counters, etc). But, increasingly, hardware design is becoming more like programming in a high level software language, like “C”. We will have a lot more to say about programming in an HDL.

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But we now know enough about the basic idea of an HDL to answer the question of the relevance of HDLs to brain building. If one wants to build artificial brains with hundreds/thousands and more of evolved neural net circuit modules, then the speed of evolution of those modules and the speed of the neural signaling of the interconnected brain comprised of those evolved modules, is paramount . It is well known that hardware speeds are typically hundreds to thousands of times faster than software speeds on the same task. As Moore’s law creates chips with millions and later billions of logic gates on a single chip, it will become increasingly possible to put artificial brain technology into them. Today’s programmable chips contain about ten million gates ( 10 7 )

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This is already enough to start putting tens of modules together to build simple artificial brains in a single chip. By placing dozens of chips on an electronic board (not cheap!) Then the size of the brain scales linearly with the number of chips. People who want to be trained in the principles of brain building technology therefore need to know how to put their brain designs into hardware, so that they can both evolve their component modules and run them once they are interconnected. Therefore, the next block of lectures will be concerned with the details of VHDL. If you have not already had a course in basic digital electronic hardware design, then you will need to quickly teach yourself these skills, because these lectures assume that knowledge.

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To teach yourself electronic design, take any number of undergrad texts on the topic. Alternatively, look at the power-point notes on this topic taught in a Master’s level course on brain building on my web site at - http://www.cs.usu.edu/~degaris/lecture-notes.html and then click on the CS6690 course. *************************************************** We begin now the more formal aspects of VHDL. These lectures are based largely on the text “VHDL Starter’s Guide”, by Sudhakar Yalamanchili, Prentice Hall, 1998, ISBN 0-13-519802-X, 270 pages.

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I have several texts on VHDL, some of them 800 pages long, e.g. “The Designer’s Guide to VHDL”. It is clear that one could spend a whole semester or more learning the finer points of VHDL design. This block of lectures therefore can only be considered an introduction to the topic. It is hoped that if you want to pursue brain building more seriously in the future, that you increase your knowledge of VHDL (or similar HDL) by yourself (by self teaching, or further courses). Why VHDL rather than Verilog? The master’s level course (see the previous slide) taught the basics of Verilog, because it is similar in format to the programming language “C”. But Verilog does not have the expressive power of VHDL, which was thought to be necessary for brain building. Hence we learn VHDL even though it is a little more difficult to use than Verilog.

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VHDL VHDL is a Hardware Description Language. Ovedr the years, HDLs have evolved to help electronic designers in the following tasks - a) Describing digital systems b) Modeling digital systems c) Designing digital systems The VHDL language can be used with several goals in mind - i) To synthesize digital circuits ii) To verify and validate digital designs iii) To generate test vectors to test circuits iv) To simulate circuits

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VHDL can be a useful means to simulate the building blocks used in digital logic and computer architecture courses. The most effective way to learn about digital systems is to build them.With VHDL, these systems can be simulated. The size of simulated systems can be larger than playing with real digital components. These lecture notes will concentrate mostly on the simulation of digital systems (using the VHDL language). VHDL Tutorials You are advised to consult the following two tutorials on VHDL on the web. The first is introductory, the second more thorough. a) http://www.connix.com/~reed/class/evita_vhdl.exe b) http://www.vhdl-online.de/%7Evhdl/TUTORIAL/

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Basic Language Concepts Digital systems are fundamentally about signals . Signals can take on 3 different values, 0, 1, or z (high impedance). Signals are analogous to wires used to connect components of a digital circuit. VHDL has a signal object type. They can be assigned values . They can have an assigned time value (since a signal takes a value at a particular time). A signal keeps its value until assigned a new one later in time. Think of a signal as a set of time-value pairs . Each pair represents some future value of the signal.

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e.g. we can model the output of an ALU an an integer value. The output can be treated as a signal and behaves as a signal by receiving values at specific points in time. However, we don’t have to concern ourselves with the number of bits necessary at the output of the ALU. We can model systems at a higher level of abstraction than digital circuits. This is useful in the early stages of circuit design, when many details of the design are still being developed. Before we can understand how to declare and operate on signals, we first must cover the basic constructs in VHDL. Entity-Architecture How to describe digital systems? (HDL = HW Description Language)

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The primary programming abstraction in VHDL is the design entity . A design entity can be e.g. a chip, board, transistor. It is a component of a design, whose behavior is to be described and simulated . Concrete example, to get the idea - Take the case of a half adder (see figure). XOR & a b sum carry A Half-Adder Circuit

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There are 2 in input signals a and b . The circuit computes the values of 2 output signals sum and carry . The half adder is an example of a design entity . How to describe accurately the half adder? There are 2 basic components to the description of a design entity - a) The external interface to the design b) The internal behavior of the design VHDL provides 2 distinct constructs to specify the external interface and the internal behavior of design entities, respectively. a) For the external interface VHDL specifies the entity declaration. b) For the internal behavior VHDL specifies the architecture declaration

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For the half adder, the entity declaration would be - entity half_adder is port (a,b: in bit ; sum, carry: out bit ); end half_adder; The highlighted (bold face) words are key words in VHDL. The other words are user given. The label half_adder is given to this design entity by the programmer. Note, VHDL is case IN sensitive . The inputs and outputs of the circuits are called PORTS . Ports are special programming objects and are signals .

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Ports are the means used by the circuit to communicate with the external world , or to other circuits . Each port , i.e. a signal , must be declared to be of a particular type . Here, each port is declared to be of type bit , and represents a single bit signal . A bit is a signal type defined within VHDL and take values 0 or 1 . A bit_vector is a signal type consisting of a vector of signals, each of type bit . Bit and bit_vector are two common types of ports. Other port data types are possible (later!) Bits and bit_vectors are fundamental signals in digital design.

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There is an IEEE 1164 Standard gaining in popularity. In it, instead of bit , the term std_ulogic is used. Similarly, instead of bit_vector , std_ulogic_vector . From now on, we use the IEEE standard notation (and data types). Hence we can rewrite the former entity declaration as - entity half_adder is port (a,b: in std_ulogic; sum, carry: out std_ulogic); end half_adder; Signals at a port can be classified as - a) Input signals b) Output signals c) Bi-directional signals

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These 3 kinds are called the mode of the signal. Bi-directional signals have the inout mode. Every port in the entity description must have its mode and type specified . Writing entity descriptions is fairly straightforward, e.g. M U X I0 I1 I2 I3 Z Sel entity mux is port (I0, I1 : in std_ulogic_vector (7 downto 0); I2, I3 : in std_ulogic_vector (7 downto 0); Sel : in std_ulogic_vector (1 downto 0); Z : out std_ulogic_vector (7 downto 0)); end mux; Entity Declaration of a 4-to-1 Multiplexor

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Clk D Q Q R S entity D_ff is port (D, Clk, R, S : in std_ulogic; Q, Qbar : out std_ulogic); end D_ff; Entity declaration of a D Flip-flop A B C Op entity ALU32 is port (A,B : in std_ulogic_vector (31 downto 0); C : out std_ulogic_vector (31 downto 0); Op : in std_ulogic_vector (5 downto 0); N, Z : out std_ulogic); end ALU32; N Z Entity Declaration of a 32-bit ALU

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From the above examples, it is clear that design entities can occur at multiple levels of abstraction , from gate level to large systems . A design entity doesn’t even have to be of digital hardware. A description of the external interface is a specification of the input and output signals of the design entity . Internal Behavior Once the interface to the digital component or circuit is described, the next thing is to describe its internal behavior . The VHDL construct used to describe an entity’s internal behavior is the architecture , whose syntax takes the general form of -

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architecture behavioral of half_adder is -- place declarations here begin -- place description of behavior here -- end behavioral; The above construct gives the declaration of the module named behavioral that contains the description of the behavior of the design entity named half_adder . Such a module is referred to as the architecture and is associated with the entity named in the declaration. Hence the description of a design takes the form of an entity-architecture pair .

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The architecture description is linked to the correct entity description by giving the name of the corresponding entity in the 1st line of the architecture . The behavioral description in the architecture can take many forms . They differ in - a) Levels of detail b) Description of events c) Degree of concurrency Concurrent Statements Electronics is inherently concurrent (i.e. many things happen at the same time), e.g. many components driving signals to new values.

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How to describe the assignment of values to signals? Signal values are time-value pairs (i.e. a signal is assigned a value at a particular time ). VHDL assigns values to signals using signal assignment statements . These statements specify a new value of a signal and the time at which the signal is to acquire this new value. Multiple signal assignment statements are executed concurrently in simulated time . These are called - Concurrent Signal Assignment statements (CSAs). There are various types of CSAs.

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Simple Concurrent Signal Assignment Consider the description of the behavior of the half-adder circuit. We need to be able to specify events , delays , and concurrency of operation of this circuit, e.g. in VHDL - architecture concurrent_behavior of half_adder is begin sum <= (a xor b) after 5 ns ; carry <= (a and b) after 5 ns ; end concurrent_behavior; The label of this architecture module is concurrent_behavior . The 1st line gives the name of the entity that describes the interface of this design entity.

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Each statement in the architecture is a signal assignment (using <= ). Each statement describes how the value of the output signal depends on, and is computed from, the values of the input signals , e.g. The value of the sum output signal is computed as the Boolean XOR operation of the two input signals. Once the value of sum has been computed, it will not change until a or b changes. In the following diagram, assume the current time is at t = 5 ns. At this time, a = 0, b = 1, and sum = 1. At t = 10 (ns), b changes to 0, so the new value of sum will be (a XOR b) = 0.

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In general, if a signal transition (called an event ) occurs on the RHS of a signal assignment statement, the expression is evaluated , and new values for the output signal are scheduled for some time in the Future (as defined by the after keyword). The dependency of the output signals on the input signals is captured in the 2 statements, and NOT in the textual order in the program. (You could reverse the order of the 2 statements, and nothing changes). Both statements are executed concurrently (with respect to simulated time). This reflects the concurrency of corresponding operations in the physical system . This is why these statements are called concurrent signal assignment statements ( CSA s). These CSAs are a major difference between VHDL and ordinary computer language (e.g. C++).

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The execution of the statements is determined by the flow of signal values and not the textual order. The following modules give a complete executable half-adder description, and the associated timing behavior . library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a,b: in std_ulogic; sum, carry: out std_ulogic); end half_adder; architecture concurrent_behavior of half_adder is begin sum <= (a xor b) after 5 ns ; carry <= (a and b) after 5 ns ; end concurrent_behavior;

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But there is a propagation delay through the XOR gate, so the signal sum will be assigned this new value 5 ns later at time 15ns. This behavior is captured in the first signal assignment statement. Signal assignment statements specify both value and (relative) time . carry 5 10 15 20 25 30 35 40ns a b sum ? ? Timing Diagram of Half-Adder

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Note the use of the library and use clauses. Libraries are repositories of frequently used design entities that we wish to share. The library clause identifies a library we wish to access. Here the library name is IEEE, but in practice it will probably map to some directory on your local system. This directory will contain various design units that have been compiled, e.g. a package (which contains definitions of types, functions, or procedures to be shared by multiple application developers (users). The use clause determines which package or design units in a library will be used in the current design.

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e.g. in the above description, the clause states that in library IEEE there is a package named std_logic_1164 and that we can use all the components defined in this package. We need this package because the definition for the type std_ulogic is in this package. VHDLs that use the IEEE 1164 value system will include the package declaration as shown. Design tool vendors usually provide the IEEE library and the std_logic_1164 package. These concepts are analogous to the use of libraries for math and I/O functions in software languages. (More on libraries and packages later in the course).

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The example contains all the major components of VHDL models, i.e. a) Declarations of existing design units in libraries you will use b) Entity description of the design unit c) Architecture description of the design unit The descriptions given so far are based on the specification of the values of the output signals as a function of the input signals, but -- In larger and more complex designs, there will be many internal signals, connecting design components, e.g. gates, or other HW building blocks. The values these internal signals can acquire can also be written with concurrent signal assignment statements (CSAs).

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So, we must be able to declare and use signals other than those within the entity description, e.g. see the full adder circuit below. X1 A1 O1 A2 X2 xor & xor & or sum c_out in1 in2 c_in s1 s2 s3 We want an accurate simulation of this circuit where all the signal transitions in the physical system are modeled. There are 3 internal signals besides the ports in the entity description (see next slide). These 3 internal signals are named and declared in the architectural description.

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library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port (in1, in2, c_in: in std_ulogic; sum, c_out: out std_ulogic); end full_adder; architecture dataflow of full_adder is signal s1, s2, s3, : std_ulogic; constant gate_delay: Time :=5 ns ; begin L1: s1<=(in1 xor in2) after gate_delay; L2: s2<=(c_in and s1) after gate_delay; L3: s3<=(in1 and in2) after gate_delay; L4: sum<=(s1 xor c_in) after gate_delay; L5: c_out<=(s2 or s3) after gate_delay; end dataflow; Architecture Body Architecture Declarative Statement

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Comments on the previous slide : We want a simulation of this circuit where all the signal transitions in the physical system are modeled. In addition to the 5 I/O ports, there are 3 internal signals. They are named and declared in the architectural description . The declarative region declares 3 single bit signals s1, s2, s3. We can now describe the behavior of the full adder in terms of the internal signals as well as the entity ports . The model is a simple statement of - a) How each signal is computed as a function of other signals. b) The propagation delay through the gate.

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There are 2 output signals and 3 internal signals , so the description consists of 5 concurrent signal assignment (CSA) statements, one for each signal. Each signal assignment is given a label , L1, L2, .. This labeling is optional (and can be used for referencing). Note the constant object. Constants in VHDL are similar to those in ordinary programming languages. A constant can have a type , e.g. Time . A constant must have a value at the start of a simulation , and cant be changed during the simulation. Initialize a constant as shown above. Any constant taking on a Time type must have values of time such as microseconds or nanoseconds .

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The type Time is a predefined type of VHDL. The textual order of the 5 CSA statements is irrelevant to the correct operation of the circuit model. Consider now the flow of signal values and the sequence of execution of the 5 CSAs. The figure below shows the wave forms of the signals in the full adder. 15 20 25 30 35 40 45ns in1 in2 sum Full-Adder Circuit Timing c_in c_out

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We see that an event on in1 at time 10, changing the value to 1. This causes statement L1 and L3 to be executed, and new values to be scheduled on signals s1 and s3 at time 15. These events in turn cause statements L2 and L5 to be executed at time 20 and events to be scheduled on signals c_out and s2 at time 20. We see that execution of the statement L1 produced events that caused the execution of statement L5. This order of execution is maintained , regardless of the textual order in which they appear in the program.

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There is a 2 stage model of execution . a) In the 1st stage, all statements with events occurring at the current time on signals on the RHS of the signal assignment statement are evaluated . b) In the 2nd stage, all future events that are generated from the execution of the statements of stage 1 are then scheduled . Time is then advanced to the time of the next event, and the above process is repeated. Note how the programmer specifies events , delays , concurrency . Events are specified with signal assignment statements . Delays are specified within the signal assignment statement . Concurrency is specified by having a distinct CSA statement per signal.

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The order of execution of the statements is dependent upon the flow of values (as with a real circuit) and not on the textual order of the program. If the programmer correctly specifies how the value of each signal is computed , and when it acquires this value relative to the current time , then the simulation will correctly reflect the behavior of the circuit. Implementation of Signals Signals are a new type of programming object, and merit special attention. So far, we have seen that signals can be declared in - a) the body of an architecture b) the port declaration of an entity

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The form of a signal declaration is - signal s1 : std_ulogic := ‘0’; or more generally, identifier-list : type := expression If the signal declaration included the assignment symbol (i.e. := ) followed by an expression, the value of the expression is the initial value of the signal. The initialization is not required, in which case, the signal is assigned with a default value depending on the type definition . Signals can be of many VHDL types, e.g. integers, real, bit_vector, …

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How to assign values to a signal? Signal assignment statements assign a value to a signal at a specific time . The simple CSAs (concurrent signal assignment) statements met so far have the following structure - sum <= (a xor b) after 5 ns ; Which can be written in a more general form as - signal <= value expression after time expression; The expression on the RHS of the signal assignment is called a waveform element .

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A waveform element describes an assignment to a signal. It consists of 2 parts - a) A value expression , to the LHS of the after keyword b) A time expression , to the RHS of the after keyword a) The value expression evaluates to the new value to be assigned to the signal. b) The time expression evaluates to the relative time at which the signal is to acquire this new value. In this case, the new value is the XOR of the current values of the signals a and b . The value of the time expression is added to the current simulation time , to determine when the signal will receive this new value .

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With respect to the current simulation time , this time-value pair represents the future value of the signal and is called a transaction . The underlying discrete event simulator that executes VHDL programs must keep track of all transactions that occur on a signal. The list is ordered in increasing time of the transactions. Can we specify multiple waveform elements ? (i.e. have several waveform elements produce several transactions on a signal). YES. e.g. s1 <= (a xor b) after 5 ns , (a or b) after 10 ns , ( not a) after 15 ns ; When an event occurs on either of the two signals a , b , then the above statement is executed, so all 3 waveform elements would be evaluated, and 3 transactions would be generated.

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Note, these transactions are in increasing time order. The events represented by these transactions must be scheduled At different times in the future. The VHDL simulator must keep track of all of the transactions Currently scheduled on a signal. This is done by maintaining an ordered list of all the current transactions pending on a signal. This list is called a driver for the signal. The current value of a signal is the value of the transaction at the head of the list . What is the physical interpretation of such a sequence of events ?

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These events represent the value of the signal over time (i.e. a waveform ). In VHDL, we can represent a waveform as a sequence of waveform elements . So, within a signal assignment statement, instead of assigning a single value to the signal at some future time, we can assign a waveform to the signal. This waveform is specified as a sequence of signal values . Each signal value is specified with a single waveform element . Within the simulator , these sequences of waveform elements are represented as a sequence of transactions on the driver of the signal .

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These transactions are called the “ projected output waveform ” because the events have not yet occurred in the simulation. What happens if the simulation tries to add transactions that conflict with the current projected waveform? VHDL has rules for adding transactions to the projected waveform of a signal. It is done as follows - e.g. Assume we want to generate the following waveform - 10 20 30 40 50 Signal transitions for each waveform element

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We can generate this waveform with the following signal assignment statement - signal <= ‘0’, ‘1’ after 10 ns , ‘0’ after 20 ns , ‘1’ after 40 ns ; Note , each transition in the above waveform is specified as a single waveform element in the signal assignment statement. All waveform elements must be ordered in increasing time , otherwise there will be a VHDL compiler error. General Remarks The concepts and terminology discussed so far are derived from the operation of digital circuits .

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There is a correspondence between a wire in a physical circuit and a driver in VHDL . Over time, the driver produces a waveform on that wire. By pursuing such analogies (i.e. the VHDL constructs, with the digital circuits the constructs are intended to model) the reasoning behind the construction of models using VHDL is made easier. The constructs that manipulate signals use waveform elements to specify input and output waveforms . Understanding this representation is key to understanding many of the VHDL programming constructs.

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Resolved Signals So far, we have thought of each signal having its own driver , i.e. one signal assignment statement that is responsible for generating the waveform on the signal. This is not true in practice. Shared signals exist on buses , and in circuits based on wired logic . When a signal has multiple drivers , how is the value of the signal determined? In VHDL, this value is determined by a resolution function . A resolution function examines all the drivers on a shared signal and determines the value to be assigned to the signal.

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A shared signal must be of a special type : a resolved type . A resolved type has a resolution function associated with the type. So far, we have been using std_ulogic , and std_ulogic_vector types for single bit and multi-bit signals respectively. The corresponding resolved types are std_logic and std_logic_vector . When a signal of type std_logic is assigned a value, the associated resolution function in automatically invoked to determine the correct value of the signal. Multiple drivers for this signal may be projecting multiple future values for this signal. The resolution function examines these drivers to return the correct value of the signal at the current time.

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If the signal has only one driver, then determination of the driver is straightforward. For the signal with multiple drivers, the value that is assigned to the signal is that determined by the resolution function . In the IEEE 1164 package, this function takes the form of a LUT (look up table), e.g. when a signal has 2 drivers, giving two signal values, the LUT returns the value to be assigned. e.g. if one source is driving the signal to 1, and the other source is left floating (i.e. in state Z, i.e. high impedance), then the result will be 1. If the 2 sources are driving the shared signal to 1 and 0, then the resulting value will be unknown , i.e. X .

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If you have multiple drivers for a signal of unresolved type, will generate an error. Users may define new resolved types, and provide the resolution functions for their use. These issues (resolution functions, etc) will be taken up in a later chapter of the text (Ch. 6, dealing with the use of procedures and Functions). For the rest of the text, all the examples use the IEEE 1164 resolved single bit and multi-bit types ( std_logic , std_logic_vector ). Conditional Signal Assignment So far, the CSAs we have seen so far compute the value of the target signal based on Boolean expressions.

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The values of the signals on the RHS are used to compute the value of the target signal. This new value is scheduled at some point in the future using the after keyword. This works fine for combinational circuits expressible with Boolean expressions. But , we need to model high-level circuits such as multiplexors (i.e. selectors ), decoders , that require a richer set of constructs. E.G. take the physical behavior of a 4-to-1, 8 bit mulitiplexor. The value of Z (the output) is one of the 4 inputs, In0, In1, In2, In3. The waveform that appears on one of the inputs is transferred to the output Z.

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The choice of which of the 4, is determined by the values of the Control signals S0, S1 (hence 4 alternatives). Each of these 4 must be tested and one chosen. This behavior is captured in the conditional signal assignment statement, e.g. library IEEE; use IEEE.std_logic_1164.all; entity mux4 is port (In0, In1, In2, In3 : in std_logic_vector (7 downto 0); S0, S1: in std_logic; Z: out std_logic_vector (7 downto 0); end mux4;

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architecture behavioral of mux4 is begin Z <= In0 after 5 ns when S0 = ‘0’ and S1 = ‘0’ else In1 after 5 ns when S0 = ‘0’ and S1 = ‘1’ else In2 after 5 ns when S0 = ‘1’ and S1 = ‘0’ else In3 after 5 ns when S0 = ‘1’ and S1 = ‘1’ else “00000000” after 5 ns ; end behavioral; The structure of the statement follows from the physical behavior of the circuit. For each of the 4 possible values of S0 and S1, a waveform is specified. The waveform is a single waveform element describing the most recent signal value on that input.

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In the corresponding physical circuit, an event on any of the 4 input signals (In0 - In 3), or on any of the control signals (S0 or S1) may cause a change in the output signal Z. Whenever any such event occurs, the CSA statement is executed, And all 4 conditions may be checked. The order of the statements is now important. The expressions in the RHS are evaluated in the order in which they appear. The first conditional expression that is true determines the value transferred to the output. Selected Signal Assignment Statement The selected signal assignment statement is very similar to the conditional signal assignment statement.

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The value of the assignment is determined by the value of a select expression . e.g. read the value of a register from a register-file of 8 registers. Depending on the address, the contents of the appropriate register are selected. Take as example, a read-only register-file with two read ports. library IEEE; use IEEE.std_logic_1164.all; entity reg_file is port (addr1, addr2 : in std_logic_vector (2 downto 0); reg_out_1, reg_out_2: out std_logic_vector (31 downto 0); end reg_file ;

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architecture behavior of reg_file is signal reg0, reg2, reg4, reg6:std_logic_vector(31 downto 0):= to_stdlogicvector(x”12345678”); signal reg1, reg3, reg5, reg7:std_logic_vector(31 downto 0):= to_stdlogicvector(x”abcdef00”); begin with addr1 select reg_out_1 <= reg0 after 5 ns when ” 000”, reg1 after 5 ns when ”001”, reg2 after 5 ns when ”010”, reg3 after 5 ns when ”011”, reg3 after 5 ns when others ; with addr2 select reg_out_2 <= reg0 after 5 ns when ” 000”, reg1 after 5 ns when ”001”, reg2 after 5 ns when ”010”, reg3 after 5 ns when ”011”, reg3 after 5 ns when others ; end behavior;

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Assume we have only 4 registers, but addr1 and addr2 are 3 bit addresses and can address up to 8 registers. VHDL requires you to specify the action to take if addr1 or addr2 takes on any of the 8 values (including those between 4 and 7). The others keyword, is used to state the value of the target signal over a range of values, and hence covers the whole range. The select expression can be quite flexible , e.g. a Boolean expression. As in a simple and conditional CSA statements, when an event occurs (i.e. on a signal used in the select expression, or in any of the signals used in one of the choices) the statement is executed . This corresponds to the expected behavior of the physical circuit, where any change in the addresses or register contents would change the value of the output signal.

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Note, there are a few new statements in the above. 1) We initialize the values of the registers when they are declared. Here, the even numbered registers are initialized with the hex value of x”12345678”, and the odd numbered registers with x”abcdef00”. Note the target is a signal of type std_logic_vector . So the hex values have to be converted to the type std_logic_vector before they can be assigned. (If the values were specified in binary notation, no explicit type conversion would be needed). The function to_stdlogicvector() is in the package std_logic_1164 and performs this type conversion. Note, there are still efforts to standardize conversions, etc. Check!

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Constructing VHDL Models Using CSAs Knowing now how to use CSAs, we can now start constructing VHDL models of interesting digital circuits/systems. This section provides a prescription (recipe) for such construction. By following this “mechanical approach” we develop an intuition about the structure of VHDL programs, and the usefulness of the constructs discussed so far. In a VHDL model using only CSAs, the execution of a signal assignment statement is initiated by the flow of data or signal values, and not the textual order of the statements. A VHDL model will consist of an entity-architecture pair .

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The architecture model will consist (probably) of combinations of simple , conditional , and selected signal assignment statements. The architecture model may also declare and use internal signals as well as the input and output ports (declared in the entity module). The following description assumes we are writing a VHDL model of a gate level , combinational circuit. The approach can also be applied to higher-level systems using combinational building blocks such as encoders, and selectors. There is a 2 step methodology - i) Draw an annotated schematic (i.e. circuit diagram). ii) Convert this to a VHDL description .

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The following procedure outlines a few steps to organize the information about the physical system before writing the VHDL model. Construct_Schematic 1) Represent each component (e.g. gate) of the system to be modeled as a delay element . The delay element captures all the delays of the computation represented by the component, and propagation of signals through the component. For each output signal of a component, associate a specific delay value through the component for that output signal.

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2) Draw a schematic interconnecting all of the delay elements . Uniquely label each component . 3) Identify the input signals of the circuit as input ports . 4) Identify the output signals of the circuit as output ports . 5) All remaining signals are internal signals . 6) Associate a type with each input, output, and internal signal, e.g. std_logic , or std_logic_vector . 7) Ensure that each input port , output port , and in internal signal is labeled with a unique name . e.g. the following schematic -----

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D D D D D Inport Ports Output Ports Internal Signal (*) * * * * From the above schematic, we can write a VHDL model using CSA statements. A template for the VHDL description now follows. This template can be filled in as will be seen shortly.

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A Template for Writing VHDL Models, Using CSAs library library-name-1, library-name-2; use library-name-1.package-name.all; use library-name-2.package-name.all; entity entity_name is port (input signals : in type; output signals : out type); end entity_name; architecture arch_name of entity_name is ---- declare internal signals ---- you may have multiple signals of different types signal internal-signal-1:type := initialization; signal internal-signal-2:type := initialization; - continued next slide -

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begin ---- specify value of each signal as a function of otaher signals internal-signal-1 <= simple, conditional, or selected CSA ; internal-signal-2 <= simple, conditional, or selected CSA ; output-signal-1 <= simple, conditional, or selected CSA ; output-signal-2 <= simple, conditional, or selected CSA ; end arch_name; Using the above template, we can now start constructing a CSA Model, using the following steps - Construct_CSA_Model 1) Use the IEEE 1164 value system, so include the 2 lines at the top of your model declaration. library IEEE; use IEEE_std_logic_1164.all

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Single bit signals can be declared to be of type std_logic , and multi-bit signals to be of type std_logic_vector . 2) Select a name for the entity (i.e. entity_name ) and write the entity description specifying each input or output signal port , its mode, and associated type. (This can be read off the annotated schematic). 3) Select a name for the architecture (i.e. arch_name ) and write the architecture description . Put the entity and architecture descriptions in the same file (actually not strictly necessary). 3.1) Within the architecture description, name and declare all the internal signals , used to connect the components. The declaration states the type of each signal and its initial value . (Initialization is not required, but is recommended). These declarations occur prior to the first begin statement in the architecture.

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3.2) Each internal signal is driven by exactly 1 component . If not , ensure that the signal is of resolved type, e.g. std_logic or std_logic_vector . For each internal signal, write a CSA statement that expresses the value of this internal signal as a function of the component input signals that are used to compute its value. Use the delay value associated with that output signal for that component. 3.3) Each output port signal is driven by the output of some internal component. For each output port signal write a CSA statement that expresses its value as some function of the signals that are inputs to that component.

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3.4) If you use any functions or type definitions provided by a 3rd party, make sure you have declared the appropriate library, using the library clause and declared the use of this package via the presence of a use clause in your model. Comments If there are S signals and ports in the schematic, there will be S CSAs in the VHDL model, one for each signal. This approach allows a quick construction of a VHDL model by maintaining a close correspondence with the HW being modeled. The above is not the only way to construct a VHDL model. With growing experience, the user will find other ways to construct interesting digital systems.

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Simulating a 1-bit ALU Consider the simple 1-bit ALU (FA = full adder) & FA OR S E L E C T O R In1 In2 c_in c_out OPCODE Result

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The result produced at the ALU output depends on the value of signal OPCODE. We write and simulate a model of this ALU using CSAs We test each OPCODE to ensure that the model is accurate by examining the waveforms on the input and output signals. We use a gate delay of 5 ns and a delay of 2 ns thru the selector (mulitiplexor) Note the OPCODE field is 2 bits wide, yet there are only 3 valid Inputs to the selector. Step 1. Follow the steps in Construct_Schematic . Ensure that all of the signals including the input and output ports are defined, labeled, and their mode and types are specified.

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Step 2. Follow the steps in Construct_CSA_Model . To describe the operation of the fulol adder, use two simple CSAs, one each to describe the computation of th sum and carry outputs respectively. Call this file alu.vhd Step 3. Compile alu.vhd Step 4. Load the simulation model into the simulator. Step 5. Generate the sequence of inputs that you can use to verify that the model is functioning correctly. Step 6. Open a trace window with the signals you would like to trace. Include internal signals which are signals that are not entity ports in the model. Step 7. Run the simulation for 50 ns .

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Step 8. Check the trace to determine correctness. Step 9. Print and record the trace. Step 10. Add new operations to the single-bit ALU, recompile, and resimulate the model, e.g. add the XOR, subtraction, and complement operations. Understanding Delays An accurate representation of digital circuit behavior requires an accurate modeling of delays thru the components. There are several delay models in VHDL, e.g. Inertial Delay Model, Transport Delay Model, Delta Delay Model. They can be incorporated easily into what has been described earlier.

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a) The Inertial Delay Model It takes a gate a finite amount of time and a certain amount of energy for the output of a gate to respond to a change on the input . This means that the change on the input has to persist for a certain period of time to ensure that the output will respond. If it does not persist long enough, the input events will not be propagated to the output. This propagation delay model is called the inertial delay model , and is the default delay model for VHDL programs. The following figure shows the application of a signal to a 2-input OR gate. If the gate delay is 8 ns, any pulse of width less than the propagation delay thru the gate is rejected .

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2 ns 8 ns Input Out1 Out2 t ns 5 10 15 20 25 30 35 OR input output Out1 is the output waveform for delay = 8 ns. Out2 is the output waveform for delay = 2 ns. If the gate delay is 8 ns , then any pulse on the input signal of duration less than 8 ns will not be propagated to the output, e.g. Out1. If the gate delay is 2 ns , then since each pulse in the input waveform is greater than 2 ns, it will be propagated to the output, e.g. Out2.

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Any pulse with a width less than the propagation delay through the gate is said to be rejected . In a physical system, whether the input signal is rejected depends on the physical design , the manufacturing parameters , etc, and is difficult to determine accurately. VHDL uses the propagation delay through the component as the default pulse rejection width . The VHDL ‘93 revision allows the format - sum <= reject 2 ns inertial (a xor b) after 5 ns ; The above statement allows a distinct pulse rejection width distinct from the propagation delay.

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This statement has the general “simple CSA” format of - signal <= reject time-expression inertial value-expression after time-expression This statement describes the occurrence of an event on a signal. It specifies - a) The value of the signal b) The time at which the signal is to receive this value c) The duration over which the input pulse must persist if the output is to receive this new value. b) The Transport Delay Model Signals propagate through wires at a finite rate and experience delays proportional to the distance .

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Unlike switches, wires have much less inertia. So wires will propagate signals with very small pulse widths. VHDL models wires to propagate any pulse width. In modern electronics, the wire delays dominate , so designs need to minimize wire length. Wire delays are non negligible , so need to be modeled to produce accurate simulations of circuit behavior. These delays are called transport delays . To specify to VHDL a transport delay, use - sum <= transport (a xor b) after 5 ns ;

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In this case, a pulse of any width on signal a or b, is propagated to the sum signal. We will generally not use the transport delay model for components with significant inertia. Example of Transport Delays So far, digital components have been treated as delay elements . Output signals acquire values after a specified propagation delay that we now know can be specified to be an inertial delay or a transport delay . If we wish to model delays along wires , we can replace the wire by a delay element .

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The delay value is equal to the delay experienced by the signal transmission along the wire, and the delay type is transport. XOR & a b sum carry s1 s2 library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a,b: in std_logic; sum, carry: out std_logic); end half_adder

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architecture transport_delay of half_adder is signal s1, s2:std_logic:=‘0’; begin s1 <= (a xor b) after 2 ns ; s2 <= (a and b) after 2 ns ; sum <= transport s1 after 4 ns ; carry <= transport s2 after 4 ns ; end transport_delay; 0 2 4 6 8 10 12 ns a b sum carry s1 s2 sum carry Inertial Transport

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Delay elements model the delay on the sum and carry signals. Note, the delay along the wires in this example is longer than the propagation delay through the gate. A pulse of width 2 ns on the sum input at time 0, is propagated to signal s1 at time 2 ns. The wire delay is 4 ns. Under the inertial delay model , this pulse would be rejected and would not appear on the sum output. But we have specified the delay to be of type transport , so the pulse is transmitted to the sum output after a delay of 4 ns. The signal is now delivered to the next circuit, having been delayed by an amount = to the propagation delay thru the signal wires .

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This approach allows accurate modeling of wire delays. In practice it is difficult to estimate wire delays without proceeding through the physical design and the layout of the circuit. The choice of using inertial delay or transport delay is determined by the components being modeled, e.g. If the model is of a board level design , we may have VHDL models of individual chips . The signal delays between chips may be modeled using the transport delay model . c) Delta Delays This section describes what happens when no delay is specified in the VHDL code.

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e.g. sum <= (a xor b); We can choose to ignore delays when - a) We don’t know what they are. b) When interested only in creating a simulation that is functionally correct but not concerned with the timing behavior. e.g. consider the timing diagram from before regarding the full_adder

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15 20 25 30 35 40 45ns in1 in2 c_in sum c_out Timing Behavior of Full_Adder There is correct ordering of events of the signals. Input events on signals in1 , in2 , and c_in produce events on internal signals s1 , s2 and s3 , which is turn produce events on the output signals sum and c_out .

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For functional correctness, this ordering must be maintained , even when delays are not specified . This is done in VHDL by defining infinitesimal delays called delta delays . The statement sum <= (a xor b) ; is given implicitly a time expression “ after 0 ns ” after the value expression. So the component is effectively given a delay value of D . Now simulation proceeds as in the previous immediate examples (i.e. with explicit delays). D does not have to be given a value, but is used within the simulator to order events .

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The simulator organizes and processes events in time order of occurrence. Events that occur D seconds later are followed by events that occur 2 D seconds later, etc. Delta delays are used to enforce dependencies between events and thereby ensure correct simulation . e.g. NOT NOT NAND NAND NAND z s3 s4 s1 s2 in1 in2

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library IEEE; use IEEE.std_logic_1164.all; entity combinational is port (in1, in2: in std_logic; z: out std_logic); end combinational architecture behavior of combinational is signal s1, s2, s3, s4:std_logic:= ‘0’; begin s1 <= not in1; s2 <= not in2; s3 <= not (s1 and in2); s4 <= not (s2 and in1); z <= not (s3 and s4); end behavior;

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in1 in2 z s1 s2 s3 s4 delta events in2 s2 s3 z 10 20 30 40 50 60 70 ns 10 D 2 D 3 D 4 D

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The events in the lower figure above are called delta events. They take place within the simulator. Summary of Basic Language Concepts 1) Entity and architecture constructs 2) Concurrent Signal Assignment statements (CSAs) simple CSAs, conditional CSAs, selected CSAs 3) Constructing models using CSAs modeling events , propagation delays , concurrency 4) Modeling delays inertial delays, transport delays, delta delays 5) Signal drivers and projected waveforms 6) Shared signals, resolved types, resolution functions 7) Generating waveforms using waveform elements 8) Events and transactions

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Modeling Behavior This topic expands on the approach used so far, that uses CSA statements for constructing VHDL models. So far, components have been modeled as delay elements , whose internal behavior is modeled with CSAs. This topic introduces more powerful constructs to describe the internal behavior of components, when they cant be modeled as delay elements. The basis fcor these more powerful descriptions is the process construct , that allows us to use conventional programming language constructs and idioms .

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a) Thus, we can model the behavior of components much more complex than delay elements - and b) We can model systems at higher levels of abstraction . =================== VHDL language and modeling concepts are derived from the operational characteristics of digital circuits. A design is represented by a schematic of concurrently operating components . Each component is characterized by the generation of events on output signals responding to events on input signals .

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The output events occur after a component-dependent signal propagation delay . The component behavior is described using a CSA statement that explicitly relates input signals , output signals , and propagation delays. Such models are convenient when components are gates or transistors. But, such models are quite limiting , when more complex components e.g. CPUs , memory modules , communication protocols , need to be modeled. The event model remains valid . (We see that events on the input signals will eventually cause events on the output signals). However, calculation of the time of occurrence and the values of the output events can be quite complex.

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For modeling memories , we need to retain state information within the component description . One cannot compute the output signal values purely as a function of the values of the input signals. E.G. consider the behavior of a model of a simple memory module, shown below - R W DO DI ADDR This memory module is provided with address, data, read/write control signals.

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Assume the memory modules contains 4096, 32-bit words of memory. The value of the R or W control signals determine whether the data on DI is written to the address on the ADDR port, OR whether data is read from that address and provided to the output port DO. Events on the input address, data, or control lines produce events that cause the memory model to be executed. We can expect to know the memory access times for read and write operations, and therefore know the propagation delays . However, the internal behavior of the memory module is difficult to describe using only the CSAs of earlier lectures!!! How to represent memory words?

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How to address the correct word, based on the values of the address lines and control signals? It is easier to get answers to the above questions if we use constructs from sequential programming languages . Memory can be implemented as an array , and the address value can be used to index this array. Depending on the value of the control signals, we can decide if this Array element is to be written or read. We can realize such behavior in VHDL by using sequential statements via the process construct. CSA statements from earlier lectures are executed concurrently .

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A VHDL model of the above memory module is shown shortly. It contains one process, that is labeled mem_process. Process labels are delimited by colons. The structure of a process is very similar to that of programs written in a conventional block structured programming language , e.g. Pascal. a) The process begins with a declarative region , followed by b) The process body , delimited by begin and end keywords Variables and constants used in the process are declared within the declarative region .

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The begin keyword denotes the start of the computational part of The process. All the statements in this process are executed sequentially. Data structures may include :- arrays, queues Programs can use standard data types, e.g. integers, characters, reals. Variable assignments take place immediately (unlike signals whose changes in values must be scheduled to occur at discrete points in time). Variable assignment is denoted by the := operator. Since all statements are executed sequentially, values assigned to variables are visible to all following statements within the same process.

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Control flow within a process is strictly sequential unless altered by constructs such as if-then-else , or loop statements. (See later lectures). You can regard the process as a traditional sequential program . The feature of a process is that we can make assignments to signals declared external to the process, e.g. In the memory model several slides ago, at the end of the process , we have signal assignment statements that assign internally computed values to signals in the interface after a specified propagation delay. Thus externally, we can maintain the discrete event execution model , events on the memory inputs produce events on the memory outputs after a delay equal to the memory access time .

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However, internally, we can develop complex models of behavior That produce these external events. With respect to simulation time , a process executes in zero time . Delays are associated only with the assignment of values to signals . library IEEE; use IEEE.std_logic_1164.all; use WORK.std_logic_arith.all; -- package for 1164 related functions entity memory is port (address, write_data: in std_logic_vector (31 downto 0); MemWrite, MemRead: in std_logic; read_data : out std_logic_vector(31 downto 0)); end memory;

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architecture behavioral of memory is type mem_array is array (0 to 7) of std_logic_vector (31 downto 0); begin mem_process: process (address, write_data) variable data_mem:mem_array:= ( to_stdlogicvector(X”00000000”), --- initialize data memory to_stdlogicvector(X”00000000”), --- to_stdlogicvector(X”00000000”), --- to_stdlogicvector(X”00000000”), to_stdlogicvector(X”00000000”), to_stdlogicvector(X”00000000”), to_stdlogicvector(X”00000000”), to_stdlogicvector(X”00000000”)); variable addr: integer ;

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begin --- the following type conversion function is in std_logic_arith addr:=to_integer(address (2 downto 0)); if MemWrite = ‘1’ then data_mem(addr):=write_data; elsif MemRead=‘1’ then read_data <= data_mem(addr) after 10 ns ; end if ; end process mem_process; end behavioral; A CSA is executed, whenever an event occurs on a signal in the RHS of the signal assignment statement. When does a process get executed?

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In the above VHDL code, next to the process keyword is a list of input signals to the component. This list is called the sensitivity list . The execution of a process is initiated whenever an event occurs on any of the signals in the sensitivity list of the process. Once started, the process executes to completion in zero ( simulation ) time and (potentially) generates a new set of events on output signals. There is a similarity between a CSA and a process - In a CSAs , the input signals are inferred from their presence in the RHS of the CSA . In a process , the input signals are in its sensitivity list .

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In effect, a process is just a “big CSA” that executes concurrently with other processes and CSAs. Processes can describe more complex events than CSAs. (Actually CSAs are processes of a simpler kind). Statements within a process are called sequential statements , since they are executed sequentially. Processes can be thought of as programs executed within a simulation to model the behavior of a component. This provides a more powerful means to model digital system behavior. These models are often called behavioral models .

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We now need to learn the syntax of the major programming constructs used within a process , e.g. a) Identifiers b) Operators c) Useful data types Programming Constructs 1) If-Then-Else An if statement is executed by evaluating an expression and conditionally executing a block of sequential statements. There may also be an else component. It is also possible to have zero or more elsif branches (note, no ‘ e ’).

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In this case, all the Boolean valued expressions are evaluated Sequentially until the first true expression is encountered. An if statement is closed with an end if clause. 2) Concurrent Processes and the Case Statement The previous example had only one process. It is possible to have concurrently executing processes. Consider the half adder, with two processes executing concurrently . Both processes are sensitive to events on the input signals a and b (i.e. when an event occurs on either a or b, both processes are activated and execute concurrently).

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library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a,b: in std_logic; sum, carry: out std_logic); end half_adder; architecture behavior of half_adder is begin sum_proc: process (a,b) begin if (a = b) then sum <= ‘0’ after 5 ns ; else sum <= (a or b) after 5 ns ; end if ; end process ;

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carry_proc: process (a,b) begin case a is when ‘0’ => carry <= a after 5 ns ; when ‘1’ => carry <= b after 5 ns ; when others => carry <= ‘X’ after 5 ns ; end case ; end process carry_proc; end behavior; ----------------------------------

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The second process above is structured using a case statement. This similar to C++’s case statement, used when it is necessary to select one of several branches of execution , based on the value of an expression. The branches of the case statement must cover all possible values of the expression being tested. Each value of the case expression can belong only to one branch of the case statement. The others clause can be used to ensure that all possible values for the case expression are covered. Usually , each branch will contain a sequence of sequential statements.

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The half adder example shows that port signals are visible within a process. This implies that process statements can read port values and can schedule values on output ports. 3) Loops There are 2 kinds of loop statements, i) for loops, and ii) while loops. i) The for loop type is used in the following example, of the multiplication of two 32-bit numbers by successively shifting the multiplicand and adding to the partial product if the corresponding bit of the multiplier is 1.

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The model saves storage by using the lower half of the 64 bit register to initially store the multiplier . As successive bits of the multiplier are examined, the bits in the lower half of the product register are shifted out, eventually leaving a 64 bit product. Note, the & operator (representing concatenation ). A logical shift right operation is specified by copying the upper 63 (out of 64) bits into the lower 63 bits of the product register, and setting the MSB (most significant bit) to 0 using the concatenater & .

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Note - a) The loop index is not declared within the process. b) The loop index is used locally for the loop. (If a variable or signal with the same name index is used elsewhere within the same process or architecture (but not the same loop), then it is treated as a distinct object. c) The loop index cannot be assigned a value or altered in the body of the loop. (So a loop index cannot be provided as a parameter via a procedure call or as an input port). ii) The while loop continue an iteration until some condition is satisfied, rather than performing a fixed number of iterations. Just replace the for statement with while (condition) loop

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Unlike the for construct, the condition can involve variables That are modified within the loop, e.g. the for loop in the Multiplication example below, could be replace with - while j< 32 loop … … j := j+1; end loop library IEEE; use IEEE.std_logic_1164.all use WORK.std_logic_arith.all -- needed for arithmetic functions

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entity mult32 is port (multiplicand, multiplier: in std_logic_vector(31 downto 0); product: out std_logic_vector(63 downto 0)); end mult32; architecture behavioral of mult32 is constant module_delay: Time := 10 ns ; begin mult_process:process(multiplicand, multiplier) variable product_register:std_logic_vector(63 downto 0):= to_stdlogicvector(X”0000000000000000”); variable multiplicand_register:std_logic_vector(31 downto 0):= to_stdlogicvector(X”00000000”);

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begin multiplicand_register := multiplicand; product_register(63 downto 0) := to_stdlogicvector(X”00000000”)&multiplier; -- repeated shift-and-add loop for index in 1 to 32 loop if product_register(0) = ‘1’ then product_register(63 downto 32) := product_register(63 downto 32) + multiplicand_register(31 downto 0); end if ;

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-- perform a right shift with zero fill product_register (63 downto 0) := ‘0’ & product_register(63 downto 1) end loop ; -- write result to output port product <= product_register after module_delay; end process mult_process; end behavioral;

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More on Processes Upon initialization , all processes are executed once !!! a) After that, processes are executed in a data-driven manner, (i.e. they are activated by events on signals in the sensitivity list of the process, or b) By waiting for the occurrence of specific events using the wait statement (see next section). Note, the sensitivity list of a process is not a parameter list ! It lists those signals to which the process is sensitive , i.e. when an event occurs on any one of these signals, the process is executed. This is similar to CSAs (which are executed whenever an event occurs on a signal on the RHS of a CSA).

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CSAs are really only processes with simpler syntax . All the ports of the entity , and the signals declared within the architecture are visible within a process - hence, a) They can be read from within a process b) They can be assigned values within a process So, during the execution of a process, it may read or write - a) Any of the signals declared in the architecture , or b) Any of the ports on the entity By this means, processes can communicate amongst themselves, e.g. Process A may write a signal that is in the sensitivity list of process B. This causes process B to execute, which in turn may write a signal that is in the sensitivity list of process A. Thus the 2 processes communicate.

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Example of Communicating Processes - the full adder . HA HA In1 In2 s1 OR c_in sum c_out s2 s3 This example shows a model of a full adder constructed from 2 half-adders and a 2 input OR gate. The behavior of the 3 components is described using processes that communicate through signals . When there is an event on either of the input signals , process HA1 executes (see code in next slide), which creates events on internal signals s1 and s2.

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But, these signals are in the sensitivity lists of processes HA2 and OR1. So, these processes will execute and schedule events on their outputs if necessary. This style of modeling follows the structural description of the HW where we have one process for each HW component . This differs from the gate level modeling style we used in earlier lectures. library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port (In1, In2, c_in : in std_logic; sum, c_out : out std_logic); end full_adder;

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architecture behavioral of full_adder is signal s1, s2, s3:std_logic; constant delay : Time := 5 ns ; begin HA1: process (In1, In2) -- process describing the 1st half adder begin s1<=(In1 xor In2) after delay; s3<= (In1 and In2) after delay; end process HA1; HA2: process (s1, c_in) -- process describing the 2nd half adder sum<=(s1 xor c_in) after delay; s2<= (s1 and c_in) after delay; end process HA2;

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OR1: process (s2,s3) -- process describing the 2 input OR gate begin c_out <= (s2 or s3) after delay; end process OR1; end behavioral; The above was a communicating process model of a full adder. --------------- Simulation Exercise - Combinational Shift Logic dataout(7 downto 0) datain(7 downto 0) shiftright shiftleft shiftnum(2 downto 0)

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Assignment # 5. This assignment constructs a combinational logic shifter. The inputs to the shift logic include - a) a 3-bit operand specifying the shift amount b) 2 single-bit signals identifying the direction of the shift (L or R) c) An 8 bit operand The output of the shift logic is the shifted 8-bit operand. Shift operations provide 0 fill, e.g. a left shift of the number 01101111 By 3 bit positions will produce the output 01111000 This assignment include the following 7 steps.

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Step 1) Create a text file with the entity description and the architecture description of the shift logic. Assume the delay through the shift logic is fixed at 40 ns (independent of the number of digits shifted). This behavior can be implemented in many ways. Here, use a single process and the sequential VHDL statements to implement the behavior of the shift logic. It is useful to use the concatenation operator & , and addressing within arrays to perform shift operations, e.g. dataout <= datain(4 downto 0) & “000”; The above assignment statement performs a left shift by 3 digits with zero fill. Both input and output operands are 8-bit numbers.

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Use the case statement to structure your process. Step 2) Use the types std_logic and std_logic_vector for the input and output signals. Declare and reference the library IEEE and the package std_logic_1164 . Step 3) Create a sequence of test vectors . Each of the test vectors will specify the values of - a) The shiftright and shiftleft single-bit control signals b) An 8-bit operand c) A 3-bit number specifying the number of digits the input operand is to be shifted. Your test cases should be sufficient to ensure the model is operating correctly. Step 4) Load the simulation model into the simulator. Set the simulator step time to be equal to the value of the propagation delay through the shift logic.

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Step 5) Using the facilities available within the simulator, generate the input stimulus and open a trace window to view both the input stimulus and output operand value. Step 6) Exercise the simulator by running the simulation long enough to cover your test cases . Verify correct operation from the trace . Step 7) Once you have the simulation functioning correctly, modify your model to implement circular shift operations, e.g. a 3 digit circular left shift takes 10010111 into 10111100. Use the concatenation operator to perform the shifts. Submit your VHDL code to the grader, plus a report on your results.

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The Wait Statement So far, our models have been data driven , i.e. events on the input signals initiated the execution of processes . Processes then do nothing until the next event on a signal defined in its sensitivity list . This kind of modeling is fine for combinational circuits, where a change in the input signals may cause a change in the output signals. Therefore the outputs should be recomputed whenever there is a change in the value of the input signal. BUT, what about modeling circuits where the output are computed only at specific points in time independent of input events?!

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How to model circuits which respond only to certain events on the input signals? e.g. In synchronous sequential circuits , the clock signal determines when the output may change , or when inputs are read . Such behavior means we need to be able to specify more generally the conditions under which the circuit outputs must be recomputed . In VHDL terms we need a more general way to specify when a process is executed or or suspended , pending on the occurrence of an event or events. This is done with the wait statement. The wait statement s explicitly specify the conditions under which a process may resume execution after being suspended.

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The forms of the wait statement include - a) wait for time expression ; b) wait on signal ; c) wait until condition ; d) wait ; Explanations : a) The first form causes suspension of the process for a period of time given by the evaluation of the time expression . The expression should evaluate to a value of type time , e.g. wait for 20 ns ;

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b) The second form causes a process to suspend execution until an event occurs on one or more signals in a group of signals, e.g. wait on clk , reset , status ; An event on any of the signals, causes the process to resume execution at the next statement after the wait statement. c) The third form specifies a condition that evaluates to a Boolean value, TRUE or FALSE. --------------------------------------- Using these wait statements, processes can be used to model components that are not necessarily data driven , but driven only by certain types of events , e.g. the rising edge of a clock signal.

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Many such conditions cannot be modeled by using sensitivity lists alone. Also, we want to construct models where we suspend a process at multiple points within the process , and not just at the beginning. Such models are possible using the wait statement. Example : Positive Edge-Triggered D Flip-Flop The D input is sampled on the rising edge of the clock, and transferred to the output. Clk D flip flop D Q Q

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So the model description must be able to specify the computations of output values only at specific points in time - i.e. the rising edge of the clock signal. library IEEE; use IEEE.std_logic_1164.all; entity dff is port (D, Clk: in std_logic; Q, Qbar: out std_logic); end dff;

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architecture behavioral of dff is begin output: process begin wait until(Clk’ event and Clk=‘1’); Q <= D after 5 ns ; Qbar <= not D after 5 ns ; end process output; end behavioral; Note the statement Clk’ event This is true if an event (i.e. signal transition) has occurred on the clock signal. The conjunction (Clk’ event and Clk = ‘1’) is true for a rising edge on the clock signal.

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The clock signal is said to have an attribute named event associated with it. (We will cover attributes next lecture). The predicate Clk’ event is true whenever an event has occurred on the signal Clk in the most recent simulation cycle. Remember, an event is a change in a signal value . A transition occurs on a signal when a new assignment has been made to the signal, but the value may not have changed. Clock Functions The std_logic_1164 package provides 2 useful functions we could use instead of attributes - a) rising_edge(Clk) b) falling_edge(Clk)

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These two functions take a signal of type std_logic as an argument and return a Boolean value denoting whether a rising edge (or falling edge ) occurred on the signal. The predicate Clk’event simply denotes a change in value. A single bit signal of type std_logic has up to 9 different values. So, if we want to model a rising edge from signal value 0 to 1, then it is better to replace the test if (Clk’ event and Clk = ‘1’) with if rising_edge(Clk) We see from the earlier VHDL code for the D flip flop that -

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a) Input is sampled on the rising clock edge. b) The output values are scheduled after a period equal to the propagation delay through the flip flop. Note, the process is not executed whenever there is a change in the value of the input signal D, but only when there is a rising edge on the signal Clk. The initial values of the flip-flop above were not specified. When a physical system is powered up, the flip flops may be initialized to some known state , but not necessarily all in the same state. It is better to have control over the initial states of the flip-flops. This is done with inputs such as Clear or Set , and Preset or Reset .

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Asserting the Set input, forces Q = 1. Asserting the Reset input, forces Q = 0. These signals override the effect of the clock signal , and are active at any time . Hence they are asynchronous inputs, as opposed to the synchronous nature of the clock signal. D flip flop D Q Q Clk R S S R Clk D Q Q 0 1 X X 1 0 1 0 X X 0 1 1 1 R 1 1 0 1 1 R 0 0 1 0 0 X X ? ?

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The R input overrides the S input. Both signals are active low . E.g. to set Q = 0, a zero pulse is applied To the reset input, while the set input is held to 1, and vice versa. During synchronous operation, both S and R must be held to 1. library IEEE; use IEEE.std_logic_1164.all; entity asynch_dff is port (R,S,D,Clk: in std_logic; Q, Qbar: out std_logic); end asynch_dff;

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architecture behavioral of asynch_diff is begin output: process (R,S, Clk) begin if (R = ‘0’) then Q <= ‘0’ after 5 ns ; Qbar <= ‘1’ after 5 ns ; elsif S =‘0’ then Q <= ‘1’ after 5 ns ; Qbar <= ‘0’ after 5 ns ; elsif (Clk’event and Clk = ‘1’) then Q <= D after 5 ns ; Qbar <= ( not D) after 5 ns ; end if; end process output; end behavioral;

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Attributes Attributes (i.e. properties) are used to return various types of information about a signal, e.g. a) determine if an event has occurred on a signal (i.e. clk’ event ) b) how much time has occurred since the last event of the signal (i.e. clk’ last_event ) When the simulator executes this statement, a function call occurs that checks the property. Such attributes are called function attributes . The next slide shows a list of useful VHDL function attributes, with - a) The name of the function attribute b) A description of the function

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1a) signal_name’ event 1b) function returning a Boolean value signifying a change in value on this signal. 2a) signal_name’ active 2b) function returning a Boolean value signifying an assignment made to this signal. This assignment may not be a new value. 3a) signal_name’ last_event 3b) function returning the time since the last event on this signal 4a) signal_name’ last_active 4b) function returning the time since the signal was last active 5a) signal_name’ last_value 5b) function returning the previous value of this signal

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There are other classes of attributes, e.g. the value attributes . These return values, e.g. the following list. 1a) scalar_name’ left 1b) returns the left most value of scalar_name in its defined range 2a) scalar_name’ right 2b) returns the right most value of scalar_name in its defined range 3a) scalar_name’ high 3b) returns the highest value of scalar_name in its defined range 4a) scalar_name’ low 4b) returns the lowest value of scalar_name in its defined range 5a) scalar_name’ ascending 5b) returns true if scalar_name has an ascending range of values

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6a) array_name’ length 6b) returns the number of elements in the array array_name Go back to our memory module. We can describe it using a new VHDL key word called type , e.g. type mem_array is array (0 to 7) of std_logic_vector (31 downto 0); (A type is (amongst other things) a way to define a composite, analogous to C++’s ADT (abstract data type). Hence mem_array’ left = 0 mem_array’ ascending = true mem_array’ length = 8

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Let us define a type that is an enumerated list, e.g. type statetype is (state0, state1, state2, state3); (This is useful for modeling state machines, (later)). So, Statetype’left = state0 Statetype’right = state3 (This is useful when we want to initialize signal values depending on their types.) Using attributes makes it easy to initialize an object to values, without knowing how it is implemented, e.g. in a state machine’s reset operation, we can initialize it to the left most state of an enumerated list of possible states, i.e. statetype’ left

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A useful attribute for arrays is range . This is useful for loop writing, in finding the index range of an array. e.g. if the array is named value_array(), then value_array’ range returns the range of the array (i.e. the number of elements in the array). So for looping - for i in value_array’ range loop … my_var := value_array(i); … end loop ;

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Generating Clocks and Periodic Waveforms Wait statements allow explicit control over reactivation of processes. They can be used to generate periodic waveforms (e.g. clock signals). We can specify several future events in a signal assignment , e.g. signal <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns; 10 20 30 40 50 ns

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If we place the above inside a process and use a wait statement, we can cause the process to be executed repeatedly , generating a periodic waveform. How? Why? 1) Remember upon initialization of a VHDL model, all processes are executed once. (So every process is executed at least once). So the first set of events will be executed. 2) Then the wait statement is executed (which reactivates the process after 50 ns (see code on next slide). This will generate events in the 50-100 ns interval. One can alter the numbers and generate a large variety of periodic signals this way.

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library IEEE; use IEEE.std_logic_1164.all; entity periodic is port (Z: out std_logic); end periodic; architecture behavioral of periodic is begin process begin Z <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns; wait for 50 ns ; end process; end behavioral;

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We can use this approach to generate a 2-phase clock . reset phi1 phi2 We show now a method to generate non-overlapping clocks and reset pulses . Such signals are very common (found in the majority of circuits). The reset process is a single CSA statement (so no need for the begin and end statements).

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library IEEE; use IEEE.std_logic_1164.all; entity two_phase is port (phi1, phi2, reset : out std_logic); end two_phase; architecture behavioral of two_phase is begin reset_process: reset <= ‘1’, ‘0’ after 10 ns; clock_process: process phi1 <= ‘1’, ‘0’ after 10 ns ; phi2 <= ‘0’, ‘1’ after 12 ns , ‘0’ after 18 ns ; wait for 20 ns ; end process clock_process; end behavioral;

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CSAs are processes, so we can assign them labels. Every process is executed at initialization just once, so the reset pulse is executed generating a pulse for 10 ns. Since the reset has no input or wait statements, the reset is never executed again! The clock process generates cycles of 20 ns. The second clock signal does not overlap with the first (by adjusting the pulse widths appropriately). The wait for statement, causes the process to be executed 20 ns later, thus repeating the cycle. This model used both concurrent and sequential statements.

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Modeling State Machines So far we have discussed only combinational and sequential circuits in isolation. Combinational circuit modeling processes are sensitive to the inputs, being activated when there is an event on an input signal. Sequential circuits retain information stored in internal devices, Such as flip-flops and latches. The values stored in these devices are called the state of the circuit. The values of the output signals can now be computed as functions of their internal state and values of the input signals.

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The values of the state variables may also change as a function of the input signals. These state variables are usually updated at discrete points in time determined by a periodic signal (e.g. a clock ). With a finite number of storage elements, the number of unique States is finite. Such circuits are called FSM s ( Finite State Machines ). Combinational Logic Inputs Outputs State s0 s1 0/1 1/0 1/0 0/1 Next state Clk

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The previous figure shows a general model of an FSM. It consists of - a) A combinational component (comprised of logic gates that compute 2 Boolean functions- i) an output function (computes the values of the output signals) ii) a next state function (computes the new values of the memory elements, i.e. the next state value). b) A sequential component (consisting of memory elements, e.g. edge triggered flip-flops that record the state and are updated synchronously by the rising edge of the clock signal). The figure on the previous slide suggests a VHDL implementation using communicating concurrent processes .

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a) The combinational component can be implemented within one process . It would be sensitive to events on the input signals and the state . So if any of the input signals or the state changes, this process will be executed to compute the values of the output signals and the new state value. b) The sequential component can be implemented with a second process . It is sensitive to the rising edge of the clock signal. When it executes, the state variables are updated with the next state computed by the combinational component. This can be modeled in VHDL as follows -

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library IEEE; use IEEE.std_logic_1164.all; entity state_machine is port (reset, clk, x : in std_logic; z : out std_logic); end state_machine; architecture behavioral of state_machine is type statetype is (state0, state1); signal state, next_state : statetype := state0;

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begin comb_process: process (state, x) begin case state is -- depending upon the current state when state0 => -- set output signals and next state if x = ‘0’ then next_state <= state1; z <= ‘1’; else next_state <= state0; z <= ‘0’; end if ;

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when state1 => if x = ‘1’ then next_state <= state0; z <= ‘0’; else next_state <= state1; z <= ‘1’; end if ; end case; end process comb_process;

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clk_process: process begin wait until (clk’ event and clk=‘1’); -- wait until the rising edge if reset = ‘1’ then -- check for reset and initialize state state <= statetype’ left ; else state<= next_state; end if ; end process clk_process; end behavioral; Analysis of the above VHDL program - The model is structured as 2 communicating processes , with state and next_state used to communicate values between them . The structure of the process comb_process is very intuitive.

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The process is constructed with a case statement. Each branch represents one of the states, and includes the output function and next_state function as shown. The process clk_process updates the state variable on the rising clock edge. On reset , this process initializes the state machine to state state0 . Note, the enumeration of state types. There is a new key word statetype , which can take values state0 or state1 The case statement describes the state machine diagram of 7 slides previously.

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In the clock process the initial state is initialized on reset using attributes. The trace of the operation of the FSM is - /clk /reset /x /z /state state0 state1 state0 /next state state1 state0 state1 state0 state1 10 ns 20 30 40

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Now that you have access to VHDL on PCs, try seeing if you can Get the same timing diagram (trace) as the figure on the previous Slide for the FSM discussed in this lecture. It will be a good exercise for you. There are 2 broad kinds of FSMs - a) Moore machines (I.e. those for which the output depends only on the current state). b) Mealy machines (I.e. those for which the output depends on both the current state AND the input). VHDL models can be made of both kinds of FSMs.