Introduction to CMS VLSI Design

Introduction to CMOS VLSI Design Scaling and Economics: 

Introduction to CMOS VLSI Design Scaling and Economics

Outline: 

21: Scaling and Economics Slide 2 Outline Scaling Transistors Interconnect Future Challenges VLSI Economics

Moore’s Law: 

21: Scaling and Economics Slide 3 Moore’s Law In 1965, Gordon Moore predicted the exponential growth of the number of transistors on an IC Transistor count doubled every year since invention Predicted > 65,000 transistors by 1975! Growth limited by power [Moore65]

More Moore: 

21: Scaling and Economics Slide 4 More Moore Transistor counts have doubled every 26 months for the past three decades.

Speed Improvement: 

21: Scaling and Economics Slide 5 Speed Improvement Clock frequencies have also increased exponentially A corollary of Moore’s Law

Why?: 

21: Scaling and Economics Slide 6 Why? Why more transistors per IC? Why faster computers?

Why?: 

21: Scaling and Economics Slide 7 Why? Why more transistors per IC? Smaller transistors Larger dice Why faster computers?

Why?: 

21: Scaling and Economics Slide 8 Why? Why more transistors per IC? Smaller transistors Larger dice Why faster computers? Smaller, faster transistors Better microarchitecture (more IPC) Fewer gate delays per cycle

Scaling: 

21: Scaling and Economics Slide 9 Scaling The only constant in VLSI is constant change Feature size shrinks by 30% every 2-3 years Transistors become cheaper Transistors become faster Wires do not improve (and may get worse) Scale factor S Typically Technology nodes

Scaling Assumptions: 

21: Scaling and Economics Slide 10 Scaling Assumptions What changes between technology nodes? Constant Field Scaling All dimensions (x, y, z => W, L, t ox ) Voltage (V DD ) Doping levels Lateral Scaling Only gate length L Often done as a quick gate shrink (S = 1.05)

Device Scaling: 

21: Scaling and Economics Slide 11 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 12 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 13 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 14 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 15 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 16 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 17 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 18 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 19 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 20 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 21 Device Scaling

Device Scaling: 

21: Scaling and Economics Slide 22 Device Scaling

Observations: 

21: Scaling and Economics Slide 23 Observations Gate capacitance per micron is nearly independent of process But ON resistance * micron improves with process Gates get faster with scaling (good) Dynamic power goes down with scaling (good) Current density goes up with scaling (bad) Velocity saturation makes lateral scaling unsustainable

Example: 

21: Scaling and Economics Slide 24 Example Gate capacitance is typically about 2 fF/ m m The FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5 f ps Estimate the ON resistance of a unit (4/2 l ) transistor.

Solution: 

21: Scaling and Economics Slide 25 Solution Gate capacitance is typically about 2 fF/ m m The FO4 inverter delay in the TT corner for a process of feature size f (in nm) is about 0.5 f ps Estimate the ON resistance of a unit (4/2 l ) transistor. FO4 = 5 t = 15 RC RC = (0.5 f ) / 15 = ( f /30) ps/nm If W = 2 f , R = 8.33 k W Unit resistance is roughly independent of f

Scaling Assumptions: 

21: Scaling and Economics Slide 26 Scaling Assumptions Wire thickness Hold constant vs. reduce in thickness Wire length Local / scaled interconnect Global interconnect Die size scaled by D c  1.1

Interconnect Scaling: 

21: Scaling and Economics Slide 27 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 28 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 29 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 30 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 31 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 32 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 33 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 34 Interconnect Scaling

Interconnect Scaling: 

21: Scaling and Economics Slide 35 Interconnect Scaling

Interconnect Delay: 

21: Scaling and Economics Slide 36 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 37 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 38 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 39 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 40 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 41 Interconnect Delay

Interconnect Delay: 

21: Scaling and Economics Slide 42 Interconnect Delay

Observations: 

21: Scaling and Economics Slide 43 Observations Capacitance per micron is remaining constant About 0.2 fF/ m m Roughly 1/10 of gate capacitance Local wires are getting faster Not quite tracking transistor improvement But not a major problem Global wires are getting slower No longer possible to cross chip in one cycle

ITRS: 

21: Scaling and Economics Slide 44 ITRS Semiconductor Industry Association forecast Intl. Technology Roadmap for Semiconductors

Scaling Implications: 

21: Scaling and Economics Slide 45 Scaling Implications Improved Performance Improved Cost Interconnect Woes Power Woes Productivity Challenges Physical Limits

Cost Improvement: 

21: Scaling and Economics Slide 46 Cost Improvement In 2003, $0.01 bought you 100,000 transistors Moore’s Law is still going strong [Moore03]

Interconnect Woes: 

21: Scaling and Economics Slide 47 Interconnect Woes SIA made a gloomy forecast in 1997 Delay would reach minimum at 250 – 180 nm, then get worse because of wires But… [SIA97]

Interconnect Woes: 

21: Scaling and Economics Slide 48 Interconnect Woes SIA made a gloomy forecast in 1997 Delay would reach minimum at 250 – 180 nm, then get worse because of wires But… Misleading scale Global wires 100 kgate blocks ok

Reachable Radius: 

21: Scaling and Economics Slide 49 Reachable Radius We can’t send a signal across a large fast chip in one cycle anymore But the microarchitect can plan around this Just as off-chip memory latencies were tolerated

Dynamic Power: 

21: Scaling and Economics Slide 50 Dynamic Power Intel VP Patrick Gelsinger (ISSCC 2001) If scaling continues at present pace, by 2005, high speed processors would have power density of nuclear reactor, by 2010, a rocket nozzle, and by 2015, surface of sun. “Business as usual will not work in the future.” Intel stock dropped 8% on the next day But attention to power is increasing [Moore03]

Static Power: 

21: Scaling and Economics Slide 51 Static Power V DD decreases Save dynamic power Protect thin gate oxides and short channels No point in high value because of velocity sat. V t must decrease to maintain device performance But this causes exponential increase in OFF leakage Major future challenge Static Dynamic [Moore03]

Productivity: 

21: Scaling and Economics Slide 52 Productivity Transistor count is increasing faster than designer productivity (gates / week) Bigger design teams Up to 500 for a high-end microprocessor More expensive design cost Pressure to raise productivity Rely on synthesis, IP blocks Need for good engineering managers

Physical Limits: 

21: Scaling and Economics Slide 53 Physical Limits Will Moore’s Law run out of steam? Can’t build transistors smaller than an atom… Many reasons have been predicted for end of scaling Dynamic power Subthreshold leakage, tunneling Short channel effects Fabrication costs Electromigration Interconnect delay Rumors of demise have been exaggerated

VLSI Economics: 

21: Scaling and Economics Slide 54 VLSI Economics Selling price S total S total = C total / (1-m) m = profit margin C total = total cost Nonrecurring engineering cost (NRE) Recurring cost Fixed cost

NRE: 

21: Scaling and Economics Slide 55 NRE Engineering cost Depends on size of design team Include benefits, training, computers CAD tools: Digital front end: $10K Analog front end: $100K Digital back end: $1M Prototype manufacturing Mask costs: $500k – 1M in 130 nm process Test fixture and package tooling

Recurring Costs: 

21: Scaling and Economics Slide 56 Recurring Costs Fabrication Wafer cost / (Dice per wafer * Yield) Wafer cost: $500 - $3000 Dice per wafer: Yield: Y = e -AD For small A, Y  1, cost proportional to area For large A, Y  0, cost increases exponentially Packaging Test

Fixed Costs: 

21: Scaling and Economics Slide 57 Fixed Costs Data sheets and application notes Marketing and advertising Yield analysis

Example: 

21: Scaling and Economics Slide 58 Example You want to start a company to build a wireless communications chip. How much venture capital must you raise? Because you are smarter than everyone else, you can get away with a small team in just two years: Seven digital designers Three analog designers Five support personnel

Solution: 

21: Scaling and Economics Slide 59 Solution Digital designers: salary overhead computer CAD tools Total: Analog designers salary overhead computer CAD tools Total: Support staff salary overhead computer Total: Fabrication Back-end tools: Masks: Total: Summary

Solution: 

21: Scaling and Economics Slide 60 Solution Digital designers: $70k salary $30k overhead $10k computer $10k CAD tools Total: $120k * 7 = $840k Analog designers $100k salary $30k overhead $10k computer $100k CAD tools Total: $240k * 3 = $720k Support staff $45k salary $20k overhead $5k computer Total: $70k * 5 = $350k Fabrication Back-end tools: $1M Masks: $1M Total: $2M / year Summary 2 years @ $3.91M / year $8M design & prototype

Cost Breakdown: 

21: Scaling and Economics Slide 61 Cost Breakdown New chip design is fairly capital-intensive Maybe you can do it for less?