Back end VLSI

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1 VLSI BACKEND TECHNOLOGY Introduction • Backend technology: fabrication of interconnects and the dielectrics that electrically isolate them. • Early structures were simple by today's standards. • More metal interconnect levels increases circuit functionality and speed. • Interconnects are separated into local interconnects (polysilicon, silicides, TiN) and intermediate/ global interconnects (Cu or Al). • Backend processing is becoming more important. • Larger fraction of total structure and processing. • Starting to dominate total speed of circuit. (From ITRS) SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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3 Back-End Technology Al Cu silicides BACK – END TECHNOLOGY ( B ack O f L ine) Front – End Technology Gate & Local interconnects will give delay with scaling global interconnects will delay !

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4 Back-End Technology_ Dimensions SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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5 Interconnects scaling larger X-sections, thicker dielectrics Global inter. delay usually 200 - 350 mm 2 C of adjacent lines C – line to substrate RC delay For min feature size F min 3 -5 nsec F min AP (A intercon R & C diel with chip area • The speed limitations of interconnects can be estimated fairly simply. • The time delay (rise time) due to global interconnects is: Dielectric constant of the oxide K ox K 1 - accounts for the fringing fields Gate delay Ex.  =3e-6Ωcm,  SiO2 =3.9, A=100mm 2 , F min =0.35µm  L =0.75ns (increases with chip A due to R) Global delay increases SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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6 Scaling: Contacts & Interconnects Global Global Self - aligned Self - aligned Self - aligned 50% delay from interconnects Earlier:15-20%, then 30-40% (delay increases with scaling)

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7 SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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8 • More sophisticated analysis from the 2003 ITRS interconnect roadmap. • Global interconnects dominate the RC delays. • “In the long term, new design or technology solutions (such as co-planar waveguides, free space RF, optical interconnect) will be needed to overcome the performance limitations of traditional interconnect.” (ITRS) Historical Development and Basic Concepts Contacts • Early structures were simple Al/Si contacts. • Highly doped silicon regions are necessary to insure ohmic, low resistance contacts. (2) • Tunneling current through a Schottky barrier depends on the width of the barrier and hence N D . • In practice, N D , N A > 10 20 are required. Delay Due to Metal 1 and Global SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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9 Aluminum Metallization high compressive stress in Al during annealing large All silicides give self-aligned contacts contact area R passive Al contact: SiO 2 native reduced good ohmic! Al 2 O 3 forms, very stable adhesion to SiO 2 Q it during annealing @ 450 0 C H formation High SS of Si in Al 0.5% 450 0 C High Si diff in Al SPIKES! in local spots Al - 2-3 µm junctions only! Ti as a sacrificed Barrier TiSi 2 & TiN (=diffusion barrier) Better solution

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10 Contacts - Electrical Parameters thermionic emission Schottky = rectifying Tunneling Surface states in Si pin F-level deep in the E-gap no metal gives f B for n – Si contact resistance & rectifying contact thermionic emission Tunneling contact Thickness of depletion = tunneling layer 2.5 nm results from N d =6. 10 19 cm -3 contact area Depends on metal/semiconductor R c [Ω]= r [Ωcm]/A[cm 2 ]  c |10 19 cm -3 =5.9•10 -2 Ωcm 2  c |10 20 cm -3 =6.7•10 -6 Ωcm 2  c ≈10 -9 Ωcm 2 will be needed Role of concentration

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11 Silicides and Polycides gate contacts local interconnects (require a-Si deposition) SALICIDE PROCESS sputtering T (~ 600 0 C ) C 49 Ti Si 2 - high resistive T ( > 800 0 C ) C 54 Ti Si 2 - low resistive Larger grains Ti also against electromigration

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12 Silicides Good adhesion Problems : adhesion stability stress large SILICON CONSUMPTION striped CoSi 2 does not cause problems with resistivity for very narrow lines

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13 • Some front-end models have also been applied to back-end processing. • Silicide formation is often modeling using the Deal-Grove linear-parabolic model. (7) • Simulation of TiSi 2 formation using FLOOPS [11.32] on a 0.35 m wide gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650˚C in a nitrogen atmosphere TiSi 2 Salicide Formation SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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14 TiSi 2 Salicide Formation Si is the diffuser for CoSi 2 TiSi 2 Creep - up short G - S Less lateral encroachment Consumption of Silicon Large : Ti Si 2 = 138 nm from Ti = 55 nm Si consumed = 125 nm fast diffusion Linear coefficient = fast reaction conductive Growth as in the oxidation process: parabolic and linear

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15 Silicide Formation and Scaling of Devices 650 0 C/ 30 ” Ar @ the top of the oxide spacer TiN growth: 20% of TiSi 2 linear growth rate 32.5 nm Ti 44 nm Si 50 nm TiSi 2 + 27 nm TiN Not all Ti consumed See Deal & Grove Linear / Parabolic growth Anneal now in N 2 2µm wide channel 0.35µm wide channel 48 nm TiSi 2 from 43 nm Si Stress important: include mechanical parameters

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16 For 1 nm of metal (Ti, Co, Ni): TiSi 2 - 2.27 nm Si used CoSi 2 - 3.64 nm Si NiSi -1.83 nm Si

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18 Electrical Measurements of Contacts gives overestimation ( R C ) of the contact properties Low resistance KELVIN BRIDGE

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19 Multilevel Metallization Non – planar surface : (1) Lithography issues depth of focus resist thinning UV light reflections (2) Step coverage & filling Use planarization FINAL GOAL FOR ADHESION & DIFFUSION BARRIER FOR ADHESION • Early two-level metal structure (early 1980’s). Non-planar topography leads to lithography, deposition, filling issues. • These issues get worse with additional levels of interconnect and required a change in structure.

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20 Planarization selective deposition GOOD PLANARITY BY FILLING VIAS

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21 Degree of planarization is (3) • One early approach to planarization incorporated W plugs and a simple etchback process. (Damascene process.) • SPEEDIE simulation below. Planarization: definition and simulation SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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22 • More advanced version of the damascene process provides both the via/contact and interconnect levels simultaneously. • In this “dual damascene” process, both the openings in the IMD for the metal interconnect and for the contact or vias underneath are opened, one after the other. • Metal is then deposited into both layers at once followed by a CMP etchback. • Interconnects have also become multilayer structures. • Shunting the Al helps mitigate electromigration and can provide mechanical strength, better adhesion and barriers in multi-level structures. TiN on top also acts as antireflection coating for lithography. Planarization Planarization A lso Helps Against Electromigration SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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23 Dielectrics • Dielectrics electrically and physically separate interconnects from each other and from active regions. • Two types: - First level dielectric - Intermetal dielectric (IMD) • First level dielectric is usually SiO 2 “doped” with P or B or both (2-8 wt. %) to enhance reflow properties. • PSG: phosphosilicate glass, reflows at 950-1100˚C • BPSG: borophosphosilicate glass, reflows at 800˚C. • SEM shows BPSG oxide layer after 800˚C reflow step, showing smooth topography over step. • Undoped SiO 2 often used above and below PSG or BPSG to prevent corrosion of Al . SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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24 ILM DIELECTRICS BPSG used for planarization

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25 • Intermetal dielectrics also made primarily of SiO 2 today, but cannot do reflow or densification anneals on pure SiO 2 because of T limitations. • Two common problems occur, cusping and voids, which can be minimized using appropriate deposition techniques. • SPEEDIE simulations of silicon dioxide depositions over a step for silane deposition (S c = 0.4) and TEOS deposition (S c = 0.1) showing less cusping in the latter case. • However planarization is also usually required today. Planarization SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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26 • One simple process involves planarizing with photoresist and then etching back with no selectivity. • Spin-on-glass (SOG) is another option: • Fills like liquid photoresist, but becomes SiO 2 after bake and cure. • Done with or without etchback (with etchback to prevent poisoned via - no SOG contact with metal). • Can also use low-K SOD’s. (spin-on-dielectrics) • SOG oxides not as good quality as thermal or CVD oxides • Use sandwich layers. • A final deposition option is HDPCVD (see chapter 9) which provides angle dependent sputtering during deposition which helps to planarize. with etchback without etchback Planarization SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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27 Planarization Techniques Reflow CMP appears as a dominating method

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28 • The most common solution today is CMP which works very well. • It is capable of forming very flat surfaces as shown in the example below. CMP SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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29 • Typical modern interconnect structure incorporating all these new features. • The biggest change that has occurred in the past 5 years is the widespread introduction of Cu, replacing aluminum. • Cu cannot be easily etched since the byproducts, copper halides are not volatile at room temperature. • Electroplating (see text section 9.3.10) plus a damascene process (single or dual) is the obvious solution and is widely used today. • Cu is the dominant material in logic chips today (µp, ASICs), but not in most memory chips. Copper Interconnects SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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30 • Backend structure showing one possible dielectric multi-structure scheme. Other variations include HDP oxide or the use of CMP. • Two backend structures. Left: three metal levels and encapsulated BPSG for the first level dielectric; SOG (encapsulated top and bottom with PECVD oxide) and CMP in the intermetal dielectrics. The multilayer metal layers and W plugs are also clearly seen. Right: five metal levels, HDP oxide (with PECVD oxide on top) and CMP in the intermetal dielectrics. Multilevel Metallization © 2000 by Prentice Hall Upper Saddle River NJ

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31 Interconnects And Vias • Al has historically been the dominant material for interconnects. - low resistivity - adheres well to Si and SiO 2 - can reduce other oxides - can be etched and deposited easily • Problems: -relatively low melting point and soft. need a higher melting point material for gate electrode and local interconnect  polysilicon. - hillocks and voids easily formed in Al. • Hillocks and voids form because of stress and diffusion in Al films. Heating places Al under compression causing hillocks. Cooling back down can place Al under tension  voids. • Adding a few % Cu stabilizes grain boundaries and minimizes hillock formation. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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32 • A related problem with Al interconnects is “electromigration.” High current density (0.1-0.5 MA/cm 2 ) causes movement of Al atoms in direction of electron flow. • Can cause hillocks and voids, leading to shorts or opens in the circuit. • Adding Cu (0.5-4 weight %) can also inhibit electromigration. • Thus Al is commonly deposited with 1-2 wt % Si and 0.5-4 wt % Cu. • Next development was use of other materials with lower resistivity as local interconnects, like TiN and silicides. • Silicides used to 1. strap polysilicon, 2. Strap junctions, 3. as a local interconnect. Electromigration SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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33 Mechanical Properties of Al protrusion of Al Al short Si O 2 may crack heating HEATING : Large thermal expansion coefficient compressive stress hillock shorts Add Cu Al diffusion by segregating @ the Al grain boundary COOLING : void formation Cu helps again Al diffusion agglomeration of Al atoms Grain boundary diffusion 0.1 – 0.5 mAcm -2 ELECTROMIGRATION --- depends on grain structure & size Cu helps - 4 wt % (avoid corrosion & etching problems ) Si added helps EM but PR

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34 Electromigration

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35 Electromigration

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36 Grain Growth

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37 THE FUTURE OF BACKEND TECHNOLOGY • Remember: (1) • Reduce metal resistivity - use Cu instead of Al. • Aspect ratio - advanced deposition, etching and planarization methods. • Reduce dielectric constant - use low-K materials. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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38 • All of these approaches are beginning to appear in advanced process flows today. Inter Level Dielectrics SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ

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39 Summary of Key Ideas • Backend processing (interconnects and dielectrics) have taken on increased importance in recent years. • Interconnect delays now contribute a significant component to overall circuit performance in many applications. • Early backend structures utilized simple Al to silicon contacts. • Reliability issues, the need for many levels of interconnect and planarization issues have led to much more complex structures today involving multilayer metals and dielectrics. • CMP is the most common planarization technique today. • Copper and low-K dielectrics are now found in some advanced chips and their use will likely be common in the future. • Beyond these materials changes, interconnect options in the future include architectural (design) approaches to minimizing wire lengths, optical interconnects, electrical repeaters and RF broadcasting. All of these areas will see significant research in the next few years. SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By Plummer, Deal & Griffin © 2000 by Prentice Hall Upper Saddle River NJ