CMOS Technology

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CMOS Technology Only 15,432,758 more mosfets to do... metal ndiff poly pdiff 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 1 Nitesh kumar

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Basic Fabrication Steps Growing silicon dioxide to serve as an insulator between layers deposited on the surface of the silicon wafer. Doping the silicon substrate with acceptor and donor atoms to create p- and n-type diffusions that form isolating PN junctions and one plate of the MOS capacitor. Depositing material on the wafer to create masks, wires and the other plate of the MOS capacitor. Etching deposited materials to create the appropriate geometric patterns. Figures are from W. Maly, Atlas of IC Technologies: An Introduction to VLSI Processes. (ignore dimensions in figures - they are quite out-of-date!) 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 2

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Growing Silicon Dioxide fast O 2 or H 2 O Surface is consumed + 900 o to 1100 o Oxygen diffuses thru SiO 2 then oxidizes Si surface Thermal oxidation creates high quality film used as mask during diffusion, insulator and gate dielectric. Local oxidation is accomplished using a Si 3 N 4 mask. Bird’s beak reduces size of unoxidized area Selective growth by using Si 3 N 4 to prevent O 2 from reaching Si surface 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 3

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Doping by Diffusion Two-step: predeposition, drive-in Constant Source Two-step process results in more uniform concentrations 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 4

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Doping by Implantation Ion implantation involves much lower process temperatures , much decreased lateral spreading and better control over dopant profile . But surface of wafer is damaged and must be repaired by subsequent thermal annealing step which will redistribute the dopants. Redistribution is minimized with special heating techniques that minimizes exposure of implanted regions. Diffusion still used when dopant profile isn’t critical. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 5

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Is there a Deposition lawsuit? Chemical vapor deposition to deposit Physical vapor deposition to SiO 2 , Si 3 N 4 , single-crystal (epitaxial) deposit metals (Al, Cu). and polycrystalline (poly) Si. Nonconformal coverage of steps leads to non-uniform thickness. In metals this can lead to higher current densities in thinner spots which causes current-induced metal migration. Modern approach: planarization. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 6

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Etching Photoresist is spun onto wafer then exposed with UV light, X- rays or electron beam (no mask). Develop to remove exposed resist. Performance note: minimum feature size often determined by photoresist and etching process. Wet etching isotropic Remove photoresist mask Dry etching anisotropic 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 7

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Sources of manufacturing problems Line registration errors resist exposure and development over/under etching, lateral diffusion uneven topography Ö systematic errors: corrected by bloating/ shrinking mask Ö random errors: increase mininum widths and spacings Mask misalignment Ö random errors: increase extensions and surrounds Other fab difficulties Ö contacts and vias only on “flat” surfaces Ö no devices near boundaries of well Ö no poly contacts over diffusion Ö “gate” metal must connect to diffusion Ö minimum metal coverage requirements Electrical properties Ö current density limitations Ö latch-up prevention Process instabilities mobility variations (why?) thin-oxide thickness variations sheet resistances Ö use of “process corners” in analysis 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 8

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Design Rules Surround rule Width rules Exclusion rule Extension rules Spacing rules We can specify the design rules using some convenient units, e.g., microns but what happens if we want to manufacture the chip using different manufacturers? One suggestion: use an abstract unit, the lambda, and scale the design to the appropriate actual dimensions when the chip is to be manufactured. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 9

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Lambda-based design rules One lambda = one half of the “minimum” mask dimension, typically the length of a transistor channel. Usually all edges must be “on grid”, e.g., in the MOSIS scalable rules, all edges must be on a lambda grid. 2x2 1 2 3 2 3 3 1 diffusion (active) poly metal1 contact 1 2 2 2 3 2x2 3 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 10

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Let’s build a CMOS inverter There are lots of different recipes to choose from. Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation hardness, reduced latch-up and substrate noise, … are all extra cost options. We’ll consider a “Chevy” process: bulk CMOS with a p-type substrate: 500 µ slice of a silicon ingot that has been doped with an acceptor (typically Use <100> surface to minimize surface charge Back is metalized to provide a good ground connection. boron) to increase the concentration of holes to 10 14 /cm 3 - 10 18 /cm 3 . p-type FETs will be embedded in the substrate, wiring goes on top Good for n-channel fets, but p-channel fets will need a n- type “well” (or tub) to live in! 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 11

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N-Well implant and drive-in The black areas of the mask show where the photoresist will be etched away, exposing the underlying material to implants or further etching. Donor atoms (e.g, P) are implanted through a window in the oxide mask and then driven-in by the next high- temp operation. The concentration is around 10 16 cm -3 and the doping profile is relatively flat. Performance note: reversed- biased PN junctions have lots of capacitance! 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 12

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PN Junctions as Insulation n p n depletion region Once the two materials are in contact, the mobile carriers move: diffusion of holes from P to N and electrons from N to P ⇒ depletion of majority carriers in boundary region. drift of majority carriers due to E field formed by fixed ions ⇒ acts in opposite direction of diffusion At equilibrium, the sum of the drift currents = sum of the diffusion currents. A depletion region is formed with a voltage across it due to induced field. At room temp, with doping concentrations of 10 15 /cm 3 , this voltage is 0.6v. The net result is a diode: I pn n p If V PN ≤ 0, the two regions are electrically isolated p V pn 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 13

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Channel-stop implant Si 3 N 4 is used to mask-off active regions (where the FETs will be built). Then a channel-stop boron implant is performed which increases acceptor concentration outside of the active regions and N-wells. Performance note: this implant leads to significant sidewall capacitance for mosfet source/drain regions. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 14

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Grow field oxide A “thick” layer of SiO 2 is formed by oxidizing the unmasked portions of the wafer with wet oxygen. This field oxide, along with the channel-stop implant, will isolate the N- and P-fets. The high temperatures used to grow the oxide also redistribute the dopants in the well, but this is usually the last high-temp operation in the fabrication process. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 15

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Grow gate oxide Now grow a “thin” (10’s of Angstroms) layer of SiO 2 , called gate oxide, on the surface -- effect on field oxide is negligible. The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the oxide, the more I DS the FET will have (we’ll see why soon) but the harder it is to make it defect- free. Performance note: thin oxides → punch-through issues → lower operating voltages → lower power dissipation but less I DS . 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 16

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Deposit polysilicon On top of the thin oxide a thick layer of polycrystalline silicon, called polysilicon or poly for short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed. Poly has a high sheet resistance of 20 Ω /sq which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi 2 ), tantalum (TaSi 2 ) or molybdenum (MoSi 2 ) => 1, 3 or 5 Ω /sq. Gate oxide Performance note: modern wire aspect ratio is more like H = 2W, so fringing fields important when calculating capacitance. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 17

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N+ source/drain implant Implant happens everywhere but source/drain region of pfets Donor implant is used to create N-fet source/drain diffusions and an ohmic N-well contact. Usually As is preferred to obtain shallow junctions and minimal lateral diffusion. High doses are N-fet source/drains needed to make low resistance are “self-aligned” with N+ well contact (25 Ω /sq) diffusion wires. poly 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 18

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P+ source/drain implant The negative (or complement) of the previous mask is used to define the p+ source/drain regions of P- fets. Boron is used as the dopant in this step. Then a short thermal annealing step is performed to repair surface damage caused by the implantation. P-fet source/drains are “self-aligned” with poly 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 19

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Grow intermediate oxide Next an intermediate oxide layer is deposited over the entire wafer using CVD (no more thermal steps please!). In modern processes, this layer is planarized using a polishing process so that the subsequent metal layers will be flat and hence have a uniform thickness. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 20

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Cut poly/diff and substrate contacts Holes (aka vias) are etched in the oxide where contacts to poly or diff are wanted (sorry, no poly contacts over gate region). The holes are filled with tungsten plugs to ensure good electrical connections. Contacts vary in resistance from .25 Ω to 10 Ω . Note that vias are usually constrained to be a particular size, so an array of vias is used when making a large “contact”. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 21

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Deposit and etch metal layer Aluminum is deposited using PVD, patterned, then etched to form low-resistance (.07 Ω /sq) interconnect. With planarization, multiple levels of metal interconnect are possible -- 3 to 5 layers are common in today’s processes. Each additional level of interconnect requires two masks: one for vias and one for forming the wires. Performance note: more layers reduces routing congestion leading to a more compact design. Sometimes layers are devoted completely to power distribution. N-channel MOSFET P-channel MOSFET 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 22

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Multiple levels of interconnect IBM photomicrograph (Si has been removed!) Metal 2 M1/M2 via Metal 1 Polysilicon Diffusion Mosfet (under polysilicon gate) 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 23

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FET = field-effect transistor The four terminals of a fet (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. gate inversion happens here E h source INVERSION: A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. drain E v bulk CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 24

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“Off” operating region V S V GS < V TH V D L Figure is from J. Rabaey, Digital Integrated Circuits The gate voltage with respect to the source (V GS ) required to form the channel is called the threshold voltage . The process engineers implant ions in the channel to achieve the chosen threshold voltage. Performance note: in small devices, there is significant IDS even when V GS < V TH (subthreshold conduction). 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 25

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“Linear” operating region V S V GS > V TH L Larger V GS creates deeper channel which increases I DS Knee due to velocity saturation and mobility degradation in small devices I DS Increasing V GS I DS ∝ ( µ n ε ox / t ox ) ( W / L ) 0 < V DS < V Dsat I DS Why isthis bigger here than on other side? Larger V DS increases drift current but also reduces vertical field component which in turn makes channel less deep. At some point, electrons are traveling as fast as possible through the channel (“velocity saturation”) and the current stops growing linearly. V DS 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 26

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Saturated operating region V S V GS > V TH V Dsat < V DS I DS L’ = L - δ L V Dsat ≡ V GS -V TH δ L This looks just like a fet with a channel When V DS = V GS -V TH the vertical field length of L’ < L. Shorter L’ implies greater I DS . As V DS increases, δ L gets larger. I DS component is reduced and the channel is pinched-off. Electrons just keep traveling across depletion region… Increasing V GS V DS 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 27

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NFET I DS curves: then and now I DS vs. V GS Figures are from J. Rabaey, Digital Integrated Circuits I DS vs. V DS Long channel Short channel 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 28

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G NFET Summary D D + G + S - S - G S D n n p V DS ≥ 0 V GS Operating regions: cut-off: V GS < V TH linear: V GS ≥ V TH V DS < V Dsat saturation: V GS ≥ V TH V DS ≥ V Dsat 0.5V S S “ V GS - V TH S I DS D linear “ D D saturation V GS V DS 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 29

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G PFET Summary D D - G + S - S + G S D p p n V DS ≤ 0 Operating regions: V GS -0.5V cut-off: V GS > V TH linear: V GS ≤ V TH V DS > V Dsat saturation: V GS ≤ V TH V DS ≤ V Dsat S D S “ “ D V GS - V TH S D -V DS -V GS saturation linear -I DS 6.371 - Fall 2002 9/18/02 L05 - CMOS Technology 30