logging in or signing up Safer PI ISIS May 00 Seattle Nickel Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 36 Category: Science & Tech.. License: All Rights Reserved Like it (0) Dislike it (0) Added: September 25, 2007 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Slide1: Model-Integrated Approach to Adaptive Embedded Systems Akos Ledeczi Institute for Software Integrated Systems Vanderbilt University Outline: Outline Key benefits of MIC Static (design-time) adaptivity Dynamic (run-time) adaptivity Conclusions Benefits of MIC: Benefits of MIC Level of abstraction: source code vs. high-level system models Constraints: implicit vs. explicit constraints Scope: point solution vs. design space System Models: System Models Domain-specific language Primarily graphical Multiple-aspects Hierarchical decomposition Model: representation of all the information that is necessary to automatically synthesize the application Constraints: Constraints Domain-specific: model-integrity constraints Application-specific: compositional resource performance cost etc. Scope: Design-Space: Scope: Design-Space Explicit alternatives andgt;andgt;andgt; finite design space Parametric, generative models: architectural parameters algorithmic description andgt;andgt;andgt; infinite design space Design-Space Exploration: Design-Space Exploration Step 1: Search-space pruning symbolic constraint satisfaction (e.g. OBDDs) interactive and iterative (selective constraint relaxation) input: 10n (n andgt;andgt; 1); output: 1-10 configurations Step 2: Simulation Step 3: Optimization Step 4: Automatic system synthesis Automatic System Synthesis: Automatic System Synthesis Hardware configuration (e.g. VHDL) Source code (C, C++, Java, SQL etc.) Configuration information: real-time schedules message routing maps assignment etc. Slide9: Target Application - Formal constraints MIC Approach System Models System Synthesis Slide10: S1 S3 S2 e1[S21]/ / /../ /../ (D1.time - D2.time) andlt; 2 P3 (mode=(S1 or S2))implies(P1=P1i) Pr1 Pr3 C1 if(k = 2 and n andlt; 4) generate(n) else generate(k) Functional models Resource models Behavior models Explicit alternatives Performance constraint Compositional constraint Hierarchical Parallel FSM G n k Generator Parameters Explicit alternatives Design Space Modeling Slide11: Design Space Pruning Slide12: Modeling objects are lost at generation step: Fixed configuration or mode-based run-time adaptivity only No incremental changes No feedback to model Static (Design-Time) Adaptivity Models Synthesis Config / source files Application Slide13: Embedded synthesizer Dynamic (Run-Time) Adaptivity Models Synthesis Application Embedded models replace (augment) configuration / source files: self-describing system incremental change capability system state is communicated in terms of model-based information Adaptive Behavior: Adaptive Behavior Monitoring Analysis, redesign, verification Reconfiguration Monitoring: Monitor variables reflect system state in the model What to monitor? Kernel/OS status Application state Events, exceptions Monitoring Embedded synthesizer Analysis, Redesign, Verification: The evaluator is a system process Varying complexity: table-driven model-defined logic procedural etc. Generator scripts: Controlled by their input parameters in the model Cannot legally be bypassed to change model Reliably handle transitions, sequencing and incremental changes Constraint manager Analysis, Redesign, Verification Embedded synthesizer R/T Executive process 2 process 3 process 4 Evaluator Constraint Manager Generator scripts Evaluator Reconfiguration: Reconfiguration Embedded synthesizer The embedded synthesizer is a system process Relatively simple translation Conclusions: Conclusions High-level system models and explicit constraints: postpone implementation decisions as late as possible Design space modeling and automatic system synthesis: amortize initial investment over the lifetime of the application Embedded models and synthesis: self-describing system You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
Safer PI ISIS May 00 Seattle Nickel Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 36 Category: Science & Tech.. License: All Rights Reserved Like it (0) Dislike it (0) Added: September 25, 2007 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Slide1: Model-Integrated Approach to Adaptive Embedded Systems Akos Ledeczi Institute for Software Integrated Systems Vanderbilt University Outline: Outline Key benefits of MIC Static (design-time) adaptivity Dynamic (run-time) adaptivity Conclusions Benefits of MIC: Benefits of MIC Level of abstraction: source code vs. high-level system models Constraints: implicit vs. explicit constraints Scope: point solution vs. design space System Models: System Models Domain-specific language Primarily graphical Multiple-aspects Hierarchical decomposition Model: representation of all the information that is necessary to automatically synthesize the application Constraints: Constraints Domain-specific: model-integrity constraints Application-specific: compositional resource performance cost etc. Scope: Design-Space: Scope: Design-Space Explicit alternatives andgt;andgt;andgt; finite design space Parametric, generative models: architectural parameters algorithmic description andgt;andgt;andgt; infinite design space Design-Space Exploration: Design-Space Exploration Step 1: Search-space pruning symbolic constraint satisfaction (e.g. OBDDs) interactive and iterative (selective constraint relaxation) input: 10n (n andgt;andgt; 1); output: 1-10 configurations Step 2: Simulation Step 3: Optimization Step 4: Automatic system synthesis Automatic System Synthesis: Automatic System Synthesis Hardware configuration (e.g. VHDL) Source code (C, C++, Java, SQL etc.) Configuration information: real-time schedules message routing maps assignment etc. Slide9: Target Application - Formal constraints MIC Approach System Models System Synthesis Slide10: S1 S3 S2 e1[S21]/ / /../ /../ (D1.time - D2.time) andlt; 2 P3 (mode=(S1 or S2))implies(P1=P1i) Pr1 Pr3 C1 if(k = 2 and n andlt; 4) generate(n) else generate(k) Functional models Resource models Behavior models Explicit alternatives Performance constraint Compositional constraint Hierarchical Parallel FSM G n k Generator Parameters Explicit alternatives Design Space Modeling Slide11: Design Space Pruning Slide12: Modeling objects are lost at generation step: Fixed configuration or mode-based run-time adaptivity only No incremental changes No feedback to model Static (Design-Time) Adaptivity Models Synthesis Config / source files Application Slide13: Embedded synthesizer Dynamic (Run-Time) Adaptivity Models Synthesis Application Embedded models replace (augment) configuration / source files: self-describing system incremental change capability system state is communicated in terms of model-based information Adaptive Behavior: Adaptive Behavior Monitoring Analysis, redesign, verification Reconfiguration Monitoring: Monitor variables reflect system state in the model What to monitor? Kernel/OS status Application state Events, exceptions Monitoring Embedded synthesizer Analysis, Redesign, Verification: The evaluator is a system process Varying complexity: table-driven model-defined logic procedural etc. Generator scripts: Controlled by their input parameters in the model Cannot legally be bypassed to change model Reliably handle transitions, sequencing and incremental changes Constraint manager Analysis, Redesign, Verification Embedded synthesizer R/T Executive process 2 process 3 process 4 Evaluator Constraint Manager Generator scripts Evaluator Reconfiguration: Reconfiguration Embedded synthesizer The embedded synthesizer is a system process Relatively simple translation Conclusions: Conclusions High-level system models and explicit constraints: postpone implementation decisions as late as possible Design space modeling and automatic system synthesis: amortize initial investment over the lifetime of the application Embedded models and synthesis: self-describing system