rm1910

Muon Group Status Report: 

Muon Group Status Report Outline: New Muon System Layout - Overview of the new Layout - Optimisation Studies - Background Studies Technology Studies - RPC R&D (Rome II) - MRPC R&D (CERN, UFRJ Rio) - WPC R&D (PNPI) - TGC R&D (Rome I) FE-Electronics - Overview of Electronics Architecture - FE-chip Summary and Conclusion

New Muon System Layout: 

New Muon System Layout Motivation: Optimization studies: - Pads in station 1 and inner part of stations 2-5 solve problem of high occupancy. - Strips in outer part of station 2-5 allow reduction of physical/logical channels and allow better granularity in x and y for stations 2 and 3. -› Improves physics performance Detector design: - New definition of regions based on realistic chambers - Regions and Pad/Strip sizes are scaling by factor 2 - Layout of station 1 similar to TP - Similar layout for stations 2 and 3 on one hand and 4 and 5 on the other Requirements to conclude on new layout: - Finalize optimization studies - Include results from Background studies - Feedback from Trigger Implementation studies - Results from matching studies (Offline) - Testbeam results for strip (pad) chambers

New Muon System Layout: 

New Muon System Layout As of today, new layout is covering slightly more than 300mrad in horizontal plane and 250 mrad in vertical plane. -› Oversize can be used to provide overlap between chambers. -› Chamber dimensions etc. should be taken as first approach only. Station 1

New Muon System Layout: 

New Muon System Layout Station 2 Station 5

New Muon System Layout: 

New Muon System Layout CPC/WPC/RPC configuration: chambers required: - CPC/WPC: 196 (Mu1) + 328 (Region 1-3 in Mu2-Mu5) 524 - RPC: ~384 (double layer Region 4 in Mu2-Mu5) Sum = 908 FE- electronics channels:

Optimization Studies: 

Optimization Studies For 2 and 3% minimum bias retention, the trigger performance (BX eff.) with the new regions is similar to the performance with the old (T.P.) regions. The performance is slightly worse for 1% minimum bias retention (new = 7.9%, old = 8.5%). Performance of new region dimensions: T.P. regions New regions

Optimization Studies: 

Optimization Studies Change aspect ratio in M2 and M3 to 0.5:2  M1 x-FOI =  2 or 3 pads M1 x-FOI FOI can ‘separate’ high p muons from B  X from low p muons from MB events Improvement in trigger performance for 1% and 2% MB retention!    Improved granularity in x in M2 and M3: M1 x now sensitive to multiple scattering (momentum)

Optimization Studies: 

Optimization Studies Summary: M1 x FOI : all other FOIs left at T.P. 3% MB retention values Purity = (muon candidates with muon hit in M3)/(all muon cadidates) Recall: Further 10% improvement in efficiency is possible if the FOIs are optimized per region.

Optimization Studies: 

Optimization Studies Trigger implementation: Several geometries have been looked at from trigger implementation point of view, running the fast identification and the theoretical algorithm Combined pad/strip layout with strips in outer part of stations 2-5, pads in station 1and inner part of stations 2-5 - same granularity as TP - 33% reduction of logical channels Algorithm efficiency for B  X: Note sensitivity to background

Background Studies: 

Background Studies Motivation: Realistic description of the background is mandatory for the - study the performance of the L0-Muon-Trigger (including safety factor) - choice of technology for the muon chambers Status: Comparison between MARS and GCALOR background calculations has been done. -› MARS gives factor ~2 higher charged particle flux prediction than GCALOR Background model has been updated, providing real particles in stations 2-5 (previously only hits) Production based on SICB version 219, using updated detector and beampipe descriptions and new physics generator started. Tentative conclusions: Conservative approach has been adapted, with background estimation based on - MARS as simulation package, - pathlength/volume as rate definition - PYTHIA event generator - Luminosity of up to 5  1032/cm2/s Impose an additional safety factor of 2-3

Background Studies: 

Background Studies Preliminary Result: For muon station 2 at R>2m one obtains with GCALOR and PYTHIA: 1  10-5/cm2/int.  400 Hz/cm2 @ 51032/cm2/s Using the conservative approach and an additional safety factor of 2 one gets ~ 4 kHz/cm2 Hit density in station 2

Testbeam Setup: 

Testbeam Setup Beam profile at PS (T11): Measured with 8cm  8cm Hodoscope

RPC R&D: 

RPC R&D Participants: Rome II RPC construction done in Italian industry (as for ATLAS and CMS) Prototypes: Single and Double Gap RPCs with - Plates of low resistivity (9  109cm) - 48cm  48cm active area - 16 strips with 3cm pitch along x and y - SMD electronics with 10  30 amplification - Gas mixture: 95% C2H2F4, 4% iso-C4H10 , 1% SF6 Status: - Beam tests done at the PS (T11) in May - Further tests in GIF in June and October - Tests on large SRPC (1m  2m) with GaAs electronics planned in November

RPC R&D: 

RPC R&D Testbeam results from the PS: Efficiency > 95% at 5kHz/cm2 Clustersize at full efficiency ~1.8 Time resolution ~2.5 ns

RPC R&D: 

RPC R&D Results from GIF-Tests GIF Photon rate: R = 740 GBq  0.85(BR)  0.5/Att.  1/4r2   Procedure: Determine R from measured plateau curve with photons R = 3.1 (1/Att)0.76 kHz/cm2 Calculate photon sensitivity factor   ~1/800

MRPC R&D: 

MRPC R&D Participants: CERN, UFRJ Rio groups Prototypes: Two small prototypes (30cm  30cm): - 4 gaps of 0.7mm - Plates of high resistivity (1011 -1012 cm), 0.7mm thick - 16 strips with 1.5 cm pitch along x - FE-chip; ASD8-B - Gas mixture: 95% C2H2F4, 4% iso-C4H10 , 1% SF6 Second prototype (230cm  130cm) : - Construction techniques have been developed Status: Beam tests done at PS (T11) in May and at the SPS (X7) in August Small prototype tested in GIF in June

MRPC R&D: 

MRPC R&D Testbeam Results: Efficiency at the PS (tspill ~400ms) Efficency vs time at the SPS No stable operating conditions for irradiations < 1s

MRPC R&D: 

MRPC R&D Testbeam Results (GIF):  ~1/200 Expectation:  ~#gaps/800 time walk: ~ 1.5ns/kV time resol.: 1.5-2 ns

WPC R&D: 

WPC R&D Participants: PNPI St.Petersburg, for new prototypes also CERN and UFRJ Rio groups Status: First WPC prototype with wire pads of different sizes has been constructed and tested in May at the PS (T11) - Gas mixture: 60% Ar , 30% CO2 , 10% CF4 - wire spacing: 1.5mm

WPC R&D: 

WPC R&D Results : Prototype performed very well No deterioration up to very high rates cross-talk: < 3% (mostly for ADC charge > ch. 4000) charge distribution time distribution

CPC and WPC R&D: 

CPC and WPC R&D Program for November Testbeam: Test of second WPC prototype with anode wire and cathode pad readout(for intermediate region in Station 1) Comparison of various FE-electronics (see later) Test of WSC prototype with anode wire and cathode strip readout - sensitive area: 16cm  150 cm - strip pitch 1cm - tests foreseen from May onwards at the PS and SPS Ongoing analysis of CPC testbeam data for small cathode pads

TGC R&D: 

TGC R&D Participants: Rome I TGC construction done in collaboration with Weizmann Institute Prototypes: Two double gap TGC - sensitive area: 25cm  80 cm - wire spacing 1.8mm, staggered - Resistance of graphite layer: ~200 k - gas mixture: 55% CO2 and 45% n-C5H12 Status: First TGC prototype has been tested in August Second prototype will be tested in November (has both pad and strip readout)

TGC R&D: 

TGC R&D Participants: Rome I TGC construction done in collaboration with Weizmann Institute Prototypes: Two double gap TGC - sensitive area: 25cm  80 cm - wire spacing 1.8mm, staggered - Resistance of graphite layer: ~200 k - gas mixture: 55% CO2 and 45% n-C5H12 Status: First TGC prototype has been tested in August Second prototype will be tested in November

TGC R&D: 

TGC R&D First Results: Note: Only one gap of tested chamber was operational Efficency > 95% up to very high rates (spot beam)

Electronics and Cables: 

Electronics and Cables Locations for electronics: Boards with a kind of ASD chip on the chambers Majority-logic and synchronization unit on the sides of the stations Muon Trigger- and- DAQ-Electronics in the Control Room Engineer from Cagliari is working on overall design for Muon FE-electronics

FE - Chip: 

FE - Chip Requirements: large variation in input capacitance (10pF - 200pF) -› in T.P. splitting of large pads has been assumed (expensive!) variation in charge collection time depending on technology (RPC  CPC) -› chip has to be adopted to the technology radiation tolerant FE-chip required even in the outer part, radiation level in inner part ~70 krad/year ! Strategy: Investigate about existing FE-chips satisfying our requirements Electronics used in Beam Tests so far: PNPI SMD electronics: (for R&D only) made of discrete components, adopted to chamber characteristics Rome I/II electronics: (for R&D only) made of discrete components, similar performance as GaAs chip (see later) ASD8-B: (8ch. bipolar chip) ~5 CHF/ch. Used in various experiments (HERA-B etc.); rather expensive.

FE-chip Candidates: 

FE-chip Candidates Favorite Candidates: SONY ASD: (4ch. bipolar chip) ~1.7 CHF/ch. Chip developed for ATLAS TGCs Peaking time @ 200pF: ~15 ns • Threshold @ 200pF: ~3 fC Sensitivity @ 0pF : ~5.6mV/fC • Noise @ 200pF: <1 fC ENC Time slewing: ~5 ns (for charge <200fC) • Radiation tolerant < 1 MRad -› Good candidate for wire chambers (TGC, WPC, WSC) -› Satisfies requirement on radiation hardness also for inner part of Mu1 GaAs chip: (8ch. 0.7m MESFET voltage amplifier) ~1.5 CHF/ch. Chip developed for ATLAS RPCs Rise/Full time: 3ns /15ns (bipolar shaping) • Threshold: ~25mV Sensitivity: ~1mV/fC • Noise: ~1 fC ENC Extremely radiation hard >100 Mrad -› Good candidate for RPCs

FE-chip Candidates: 

FE-chip Candidates Other Developments: Minsk ASD: (8ch. bipolar chip) ~1.6 CHF/ch. Peaking time @ 100pF: ~15 ns • Threshold @ 75pF: ~5 fC Sensitivity @ 100pF : 5-10mV/fC • Noise @ 100pF: <1 fC ENC Time slewing: ~4 ns Radiation hardness tested so far only for preamp, not the full chip(~1 Mrad) -› Possible candidate for wire chambers (but Cin not very good) -› Tests foreseen in October/November GaAs chip: (8ch. 0.7m MESFET) Adaptation of GaAs chip for wire chambers has started (charge amplifier) The goal is to reproduce performance of SONY chip -› Possible candidate for wire chambers -› First samples foreseen sometime in spring -› New Developments should not prevent a baseline decision on the FE-chip in January 2000

Summary and Conclusion: 

Summary and Conclusion Muon System Layout: A realistic and optimized layout has been found and is currently finalized/checked from point of view of robustness and performance. Detector Technology Studies: An extensive testbeam program for RPC studies had been done. Encouraging results have been obtained. A WPC prototype has been tested and good performance has been obtained. Tests of WPC and TGC prototypes with cathode pad/strip readout are ongoing. FE-chip Studies: FE-chips satisfying the requirements for the various detector technologies have been found and will be tested on the prototypes in the forthcoming weeks. -› All the input for the decisions due in January 2000 should be available in a few weeks.