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Effective Post-Programming Screening of Antifuse FPGAs for Space Applications Yasuo Sakaide, Kimiharu Kariu, Kenji Numata, Akihisa Tsukino, Mikihiko Urano, Kenichi Chiba, Kenji Sugimoto, Yoshihisa Tsuchiya, Toshifumi Arimitsu Y. Sakaide High-Reliability Components Corporation

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Abstract For a decade, HIREC has been working for post-programming screening of antifuse FPGAs and supplying the FPGAs to Japanese space customers, meeting with the full technical satisfactions. In this paper, we report the results on the effectiveness of the post-programming screening for antifuse FPGAs to ensure the reliable use of the FPGAs.

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• design (MPU, Memory, FPGA, etc.) Introduction of HIREC HIREC is a test house qualified by JAXA (Japan Aerospace Exploration Agency) • quality assurance (surveillance, source inspection, etc.) • screening and quality conformance inspection • environmental test (radiation test, etc.) • Destructive physical analysis, construction analysis and failure analysis (SEM inspection, etc.) for semiconductor devices (MPU, Gate Array, Memory, etc. ) for space applications. performs design of semiconductor devices for space application.

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1. Purpose of post-programming screening Post-Programming Electrical   Parameter Test (PPEPT) To ensure the electrical parameters as a built configuration. Actual delay parameters cannot be measured for blank devices. Programming instruments doesn’t assure the electrical performance (i.e. functionality, timing, and so forth ) in full operating range. Because: PPEPT is necessary for programmed antifuse FPGAs. (2) Post-Programming Dynamic    Burn-In (PPDBI) To screen the potential damage to internal logic elements during device programming. High programming voltage (Vpp) may damage the internal logic elements. Dynamic burn-in is the most effective way to exercise all the active elements as a built configuration. Because: PPDBI is necessary for programmed antifuse FPGAs.

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HIREC Post-programming screening flow Notes: (1) Pre Burn-In electrical parameters tests are measured for Subgroup 1, 7, and 9.      (2) Interim (Final) electrical parameters tests are measured for Subgroup 1, 7 and        9(1,2,3,7,8,9 and 10) listed on MIL-PRF-38535, TableⅢ.      (3) Delta calculation is performed for the parameters specified in SMD.      (4) Option.

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Electrical parameters test system in HIREC LSI test system An example of DUT board Dynamic burn-in test system in HIREC Full dynamic burn-in system An example of burn-in board

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2. Results of post-programming screening Post-programming screening summary performed in HIREC (a)~(e) means fail mode on electrical parameters as shown below; (a)・・・Standby supply current (IDD(STB)) (b)・・・Input leakage current (IIL/IIH) (c)・・・Functional Test (FT) (“Functionality” only for PPDBI) (d)・・・Output voltage (VOL/VOH) (e)・・・All parameters

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2.Results of post-programming screening (cont.) (2) Pre burn-in electrical parameters test at 25ºC by LSI tester. ・ The instruments cannot ensure the quality/reliability of programmed FPGAs.   Standby supply   current (IDD(STB)) RP1280A (1pc.) RT14100A (1pc.) RT54SX32 (1pc.) RT54SX32S (3pcs.)   Input leakage   current (IIL/IIH) A1280A (1pc.) RP1280A (1pc.) RH1280 (1pc.)   Functional test   (FT) A1280A (1pc.) RT14100A (1pc.) RT54SX32 (1pc.) Summary of programming performed in HIREC Total 3019 pcs. Total 100 pcs. Note: There are 2 designs whose number of failures exceeded the maximum number of allowed programming failures defined by the manufacturer. Failure Programming (1) Programming

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(5) Delta calculation Anomalous delta for IDD(STB) for the same designed RT54SX16 (4pcs. from 4pcs.) Anomalous delta for IDD(STB) for the same designed RH1280 (1pcs. from 4pcs.) Anomaly of Functionality and Operating current during burn-in A1280A (1pc.) RH1280 (1pc.) Standby supply current RT54SX16 (1pc.) Catastrophic damage A1280A (1pc.) Standby supply current   RT54SX16 (3pcs.)      RH1280 (1pc.) (4)Final electrical   parameters test at 25 ºC (3)Post- Programming   Dynamic Burn-In   (PPDBI)

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S/N 2061 failed the input leakage current (IIL/IIH) at +125ºC for the same designed RP1280A (6) Final electrical   parameters test   at -55 and +125ºC   Input leakage current (IIH) RT54SX16 (1pc.)   Functional test (FT) RT14100A (3pcs.)   Output voltage (VOH) RT54SX16 (4pcs.)    All parameters RP1280A (1pc.)

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4.Conclusion The post-programming screening has revealed that some portion of the antifuse FPGAs were defective after programming. The schedule and costs might be strongly affected, if the above problems are discovered on the FPGAs embedded in the flight hardware. The post-programming screening for antifuse FPGAs is mandatory for space applications.

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