Memory Interfacing with 8085 Microprocessor

Views:
 
Category: Education
     
 

Presentation Description

What is an Interface, Pins of 8085 used in Interfacing, Memory – Microprocessor Interface, I/O – Microprocessor Interface, Basic RAM Cells, Stack Memory.

Comments

Presentation Transcript

Memory and I/O Interfacing:

Memory and I/O Interfacing Subject: Microprocessors Class: 4 th Sem ECE Presented By Kulwinder Singh Lecturer ECE S. R. S. Govt Polytechnic College for Girls Ludhiana Email: kulwinderpannu@gmail.com Mobile: 97813-00151 22-02-2012 1 of 55 PUNJAB EDUSAT SOCIETY (PES)

Index:

Index What is an Interface Pins of 8085 used in Interfacing Memory – Microprocessor Interface I/O – Microprocessor Interface Basic RAM Cells Stack Memory. 22-02-2012 2 PUNJAB EDUSAT SOCIETY (PES)

What is an Interface:

What is an Interface an interface is a concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software. This allows a component, (such as a graphics card or an Internet browser ), to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol . 22-02-2012 3 PUNJAB EDUSAT SOCIETY (PES)

Example Block Diagram:

Example Block Diagram 8085 Memory Address Lines Data Lines Control Lines Interface 22-02-2012 4 PUNJAB EDUSAT SOCIETY (PES)

8085 Interfacing Pins:

8085 Interfacing Pins 8085 Higher Address Bus Lower Address/Data Bus ALE READY A 15 – A 8 AD 7 – AD 0 22-02-2012 5 PUNJAB EDUSAT SOCIETY (PES)

Address Bus of 8085:

Address Bus of 8085 Address Bus Used to address memory & I/O devices 8085 has a 16-bit address bus A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 Lower-order Address Higher-order Address Data Bus Used to transfer instructions and data 8085 has a 8-bit data bus Data Bus 22-02-2012 6 PUNJAB EDUSAT SOCIETY (PES)

Higher Order Address Bus:

Higher Order Address Bus The higher order address bus is a unidirectinal bus. It carries most significant 8-bits of a 16-bit address of memory or I/O device. Address remains on lines as long operation is not completed. 22-02-2012 7 PUNJAB EDUSAT SOCIETY (PES)

Lower Order Address/Data Bus:

Lower Order Address/Data Bus This bus is bidirectional and works on time division multiplexing between address and data. During first clock cycle, it serves as a least significant 8-bits of memory/ IO address. For second and third clock cycles it acts as data bus and carries data. 22-02-2012 8 PUNJAB EDUSAT SOCIETY (PES)

Demultiplexing Address/Data Lines:

Demultiplexing Address/Data Lines 8085 identifies a memory location with its 16 address lines, (AD0 to AD7) & (A8 to A15) 8085 performs data transfer using its data lines, AD0 to AD7 Lower order address bus & Data bus are multiplexed on same lines i.e. AD0 to AD7. Demultiplexing refers to separating Address & Data signals for read/write operations. 22-02-2012 9 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Need for Demultiplexing… 8085 Memory 20H 05H 2005H A 15 – A 8 AD 7 – AD 0 4FH 22-02-2012 10 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

22-02-2012 11 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Demultiplexing Address/Data Lines 8085 Memory Interface Memory Chip AD0-AD7 Control A0 – A7 Data 74LS373 A8-A15 A8-A15 ALE 22-02-2012 12 PUNJAB EDUSAT SOCIETY (PES)

Generating Control Signals:

Generating Control Signals Memory Read Memory Write IO Read IO Write RD=0 WR=1 =0 1 1 0 0 1 1 0 0 22-02-2012 13 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Generating Control Signals Memory Read Memory Write IO Read IO Write RD=1 WR=0 =0 1 1 0 0 0 0 1 1 22-02-2012 14 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Generating Control Signals Memory Read Memory Write IO Read IO Write RD=0 WR=1 =1 0 0 1 1 1 1 0 0 22-02-2012 15 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Generating Control Signals Memory Read Memory Write IO Read IO Write RD=1 WR=0 =1 0 0 1 1 0 0 1 1 22-02-2012 16 PUNJAB EDUSAT SOCIETY (PES)

Memory Interface:

Memory Interface The memory is made up of semiconductor material used to store the programs and data. The types of memory is, Primary or main memory Secondary memory 22-02-2012 17 PUNJAB EDUSAT SOCIETY (PES)

Primary Memory:

Primary Memory RAM and ROM are examples of this type of memory. Microprocessor uses it in storing a program temporarily (commonly called loading) and executing a program. Hence the speed of this type of memory should be fast. 22-02-2012 18 PUNJAB EDUSAT SOCIETY (PES)

Secondary Memory:

Secondary Memory These are used for bulk storage of data and information. The main examples include Floppy, Hard Disk, CD-ROM, Magnetic Tape etc. Slower and Sequential Access Nature. non-volatile nature. 22-02-2012 19 PUNJAB EDUSAT SOCIETY (PES)

Memory Chip:

Memory Chip Memory 2n words ‘k’ bits per word ‘k’ data input lines ‘k’ data output lines ‘n’ address lines read write Chip select 22-02-2012 20 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

8085 Interfacing with Memory chips 8085 Memory Interface Program Memory AD0-AD7 IO/M A0 – A7 Data 74LS373 A8-A15 A8-A15 ALE RD RD CS 22-02-2012 21 PUNJAB EDUSAT SOCIETY (PES)

Interface with two memory chips:

Interface with two memory chips 11 10 01 00 11 10 01 00 A 0 A 1 Memory 1 Memory 2 22-02-2012 22 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

Interface with two memory chips 11 10 01 00 11 10 01 00 A 0 A 1 Memory 1 Memory 2 A 3 011 010 001 000 111 110 101 100 22-02-2012 23 PUNJAB EDUSAT SOCIETY (PES)

Interface with Multiple Chips:

Interface with Multiple Chips In case of multiple chips simple circuit like NOT gate will not work. In this case normally decoder circuits like 3-to-8 decoder circuit 74LS138 are used. These circuit are called address decoders. 22-02-2012 24 PUNJAB EDUSAT SOCIETY (PES)

Address decoders:

Address decoders Memory 1 Memory 2 Memory 3 Memory 4 A 12 A 11 A 10 - A 0 S 1 S 0 E A 13 O 0 O 1 O 2 O 3 2 to 4 decoder 22-02-2012 25 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

The Overall Picture A15-A8 Latch AD7-AD0 D 7 - D 0 A 7 - A 0 8085 ALE IO/M RD WR 1K Byte Memory Chip WR RD CS A 9 - A 0 A 15 - A 10 Chip Selection Circuit 22-02-2012 26 PUNJAB EDUSAT SOCIETY (PES)

Types of Address Decoding:

Types of Address Decoding There are two types of address decoding techniques Exhaustive Decoding Partial Decoding 22-02-2012 27 PUNJAB EDUSAT SOCIETY (PES)

Exhaustive Decoding:

Exhaustive Decoding In this type of scheme all the 16 bits of the 8085 address bus are used to select a particular location in memory chip. Advantages: Complete Address Utilization Ease in Future Expansion No Bus Contention, as all addresses are unique. Disadvantages Increased hardware and cost. Speed is less due to increased delay. 22-02-2012 28 PUNJAB EDUSAT SOCIETY (PES)

Partial Decoding:

Partial Decoding In this scheme minimum number of address lines are used as required to select a memory location in chip. Advantages: Simple, Cheap and Fast. Disadvantages: Unutilized space & fold back (multiple mapping). Bus Contention. Difficult future expansion. 22-02-2012 29 PUNJAB EDUSAT SOCIETY (PES)

Interfacing I/O Devices:

Interfacing I/O Devices Using I/O devices data can be transferred between the microprocessor and the outside world. This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O. The other method is serial I/O where one bit is transferred at a time using the SID and SOD pins on the Microprocessor. 22-02-2012 30 PUNJAB EDUSAT SOCIETY (PES)

Types of Parallel Interface:

Types of Parallel Interface There are two ways to interface 8085 with I/O devices in parallel data transfer mode: Memory Mapped IO IO Mapped IO 22-02-2012 31 PUNJAB EDUSAT SOCIETY (PES)

Memory Mapped IO:

Memory Mapped IO It considers them like any other memory location. They are assigned a 16-bit address within the address range of the 8085. The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory. 22-02-2012 32 PUNJAB EDUSAT SOCIETY (PES)

IO Mapped IO:

IO Mapped IO It t reats them separately from memory. I/O devices are assigned a “port number” within the 8-bit address range of 00H to FFH. The user in this case would access these devices using the IN and OUT instructions only. 22-02-2012 33 PUNJAB EDUSAT SOCIETY (PES)

IO mapped IO V/s Memory Mapped IO:

IO mapped IO V/s Memory Mapped IO Memory Mapped IO IO is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 2 16 =64k locations. Less memory is available. IO Mapped IO IO is treated IO. 8- bit addressing. Less Decoder Hardware. Can address 2 8 =256 locations. Whole memory address space is available. 22-02-2012 34 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

IO mapped IO V/s Memory Mapped IO Memory Mapped IO Memory Instructions are used. Memory control signals are used. Arithmetic and logic operations can be performed on data. Data transfer b/w register and IO. IO Mapped IO Special Instructions are used like IN, OUT. Special control signals are used. Arithmetic and logic operations can not be performed on data. Data transfer b/w accumulator and IO. 22-02-2012 35 PUNJAB EDUSAT SOCIETY (PES)

The interfacing of output devices:

The interfacing of output devices Output devices are usually slow. Also, the output is usually expected to continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally. 22-02-2012 36 PUNJAB EDUSAT SOCIETY (PES)

The interfacing of output devices:

The interfacing of output devices To do this the external latch should be enabled when the port’s address is present on the address bus, the IO/M signal is set high and WR is set low. The resulting signal would be active when the output device is being accessed by the microprocessor. Decoding the address bus (for memory-mapped devices) follows the same techniques discussed in interfacing memory. 22-02-2012 37 PUNJAB EDUSAT SOCIETY (PES)

Interfacing of Input Devices:

Interfacing of Input Devices The basic concepts are similar to interfacing of output devices. The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IORD signal is generated by combining the IO/M and the RD signals from the microprocessor. 22-02-2012 38 PUNJAB EDUSAT SOCIETY (PES)

Interfacing of Input Devices:

Interfacing of Input Devices A tri-state buffer is used to connect the input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IORD. 22-02-2012 39 PUNJAB EDUSAT SOCIETY (PES)

Basic RAM Cell:

Basic RAM Cell RAM is a type of computer memory that can be accessed randomly i.e. any location can be accessed any time within chip. It is most common type of memory found in computers, printers etc. It is basically of two types: SRAM DRAM 22-02-2012 40 PUNJAB EDUSAT SOCIETY (PES)

SRAM:

SRAM SRAM stands for Static Random Access Memory. This memory is made up of flip-flops and stores the bit as a voltage. Each cell requires 6 transistors hence chip has low density but high speed. More expensive and consumes more power. Often known as cache memory in high speed PCs. 22-02-2012 41 PUNJAB EDUSAT SOCIETY (PES)

Basic SRAM Cell:

Basic SRAM Cell 22-02-2012 42 PUNJAB EDUSAT SOCIETY (PES)

DRAM:

DRAM DRAM stands for Dynamic Random Access Memory. This memory is made up of MOS transistor gates and it stores the bit as charge. High density, low power consumption, cheap as compared to SRAM. Due to leakage of charge requires frequent refreshing and hence extra circuitry. 22-02-2012 43 PUNJAB EDUSAT SOCIETY (PES)

Basic DRAM:

Basic DRAM 22-02-2012 44 PUNJAB EDUSAT SOCIETY (PES)

ROM:

ROM ROM is a read only memory. It retains the information even if power is turned off. It contains permanently stored instructions that help in staring up of a computer e.g. BIOS or Basic Input Output System. These are of following three basic types PROM, EPROM, EEPROM 22-02-2012 45 PUNJAB EDUSAT SOCIETY (PES)

PROM:

PROM The Programmable Read Only Memory can be programmed only once in its lifetime. Information once stored can not be erased. Requires special hardware circuit to program it. 22-02-2012 46 PUNJAB EDUSAT SOCIETY (PES)

EPROM:

EPROM Stands for Erasable Programmable Read Only Memory. These ROMs can be erased and programmed again and again. Can be erased with UV light or electricity. Main disadvantage is that it takes 15 to 20 minutes to erase it. 22-02-2012 47 PUNJAB EDUSAT SOCIETY (PES)

EEPROM:

EEPROM Stands for Electrically Erasable Programmable Read Only Memory. Information can be erased electrically at register level rather than erasing entire information. It requires lesser erasing time. 22-02-2012 48 PUNJAB EDUSAT SOCIETY (PES)

Stack:

Stack It is a part of memory, reserved in RAM, used to temporarily store information during execution of program. Starting address of stack is loaded in “Stack Pointer (SP)” (a 16-bit register). The address pointed to by SP is known as “Top of Stack”, which is always an empty memory location. 22-02-2012 49 PUNJAB EDUSAT SOCIETY (PES)

Stack Initialization:

Stack Initialization Stack can be defined anywhere in RAM. But generally it initialized from highest (end) address of RAM to avoid any data loss. FFFFH F000H 0000H STACK MEMORY SP = FFFFH TOP OF STACK 22-02-2012 50 PUNJAB EDUSAT SOCIETY (PES)

Size of Stack Memory:

Size of Stack Memory Theoretically there is no limitation on the size of stack memory. Practically the size of stack memory is limited to the availability of free RAM. As RAM is used to store temporarily program and data during execution, hence only free RAM can be used as stack. 22-02-2012 51 PUNJAB EDUSAT SOCIETY (PES)

Storing Data on Stack:

Storing Data on Stack Stack is Last-In-First-Out (LIFO) type of memory. When information is stored on stack, the Stack Pointer register decrements to point to lower empty address. When information is read from stack, the Stack Pointer register increments to point to higher empty address. 22-02-2012 52 PUNJAB EDUSAT SOCIETY (PES)

Animation Stack Memory:

Animation Stack Memory FFFF FFFE FFFD FFFC FFFB FFFA FFF9 0001 0000 STACK MEMORY PUSH B Stack Pointer PUSH C POP B POP C 52 H B= 52 H FFFF H FFFE H 35 H C = 35 H FFFD H 35 H 52 H 22-02-2012 53 PUNJAB EDUSAT SOCIETY (PES)

Advantages of Stack:

Advantages of Stack Address is always in Stack Pointer, need not be part of instruction, therefore, stack access is always faster. Stack instructions are short with only one operand. Used to save important data before branch instruction e.g. jump or interrupt instruction. 22-02-2012 54 PUNJAB EDUSAT SOCIETY (PES)

PowerPoint Presentation:

THANKS 22-02-2012 55 PUNJAB EDUSAT SOCIETY (PES)

authorStream Live Help