# Counters

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Category: Education

## Presentation Description

Introduction to digital counters, ripple, synchronous counters, up-down counters, ring counter

## Presentation Transcript

### Digital Counters:

Digital Counters Subject: Digital Electronics Class: 3 rd Sem ECE Presented By Kulwinder Singh Lecturer ECE S. R. S. Govt Polytechnic College for Girls Ludhiana Email: kulwinderpannu@gmail.com 3/31/2013 Punjab Edusat Society (PES) 1 of 60

### Counter:

Counter Counter is one of the most useful and versatile circuit used in a digital system. It is commonly used to accomplish following tasks: To count number of pulses To divide a frequency To generate address of memory locations 3/31/2013 Punjab Edusat Society (PES) 2 of 60

### JK Flip Flop:

JK Flip Flop J K Q n Ǭ FFA Clk Inputs Clock Outputs Comments J K Q n+1 Ǭ n+1 0 0 Q n Ǭ n Previous state 0 1 0 1 Reset 1 0 1 0 Set 1 1 Ǭ n Q n Toggle 3/31/2013 Punjab Edusat Society (PES) 3 of 60 + ve edge triggered - ve edge triggered Level triggered

### Modulus of a Counter:

Modulus of a Counter Total number of counts or ‘Stable States’ of a counter circuit is known as its MODULUS or simply MOD. For example MOD of a 4-bit binary counter which counts from 0000 to 1111 is 16. And for 3-bit binary counter MOD is 8. 3/31/2013 Punjab Edusat Society (PES) 4 of 60

### Types of Counters:

Types of Counters Counters are basically a series of flip-flops wired together to perform desired type of counting. Counters are broadly classified into two types Asynchronous or Ripple Counters Synchronous Counters 3/31/2013 Punjab Edusat Society (PES) 5 of 60

### Asynchronous Counters:

Asynchronous Counters These are called asynchronous counters because flip-flops in the circuit are not driven by a common clock, instead are tied to outputs of other flip-flops. Hence operate in the form of chain reaction or ripple, therefore are also known as ripple counters. 3/31/2013 Punjab Edusat Society (PES) 6 of 60

### Count Sequence:

Count Sequence B A 0 0 0 1 1 0 1 1 0 0 3/31/2013 Punjab Edusat Society (PES) 7 of 60 Note that flip flop B changes state on negative edge transition of flip flop A.

### Construction of Asyn. Counter:

Construction of Asyn . Counter To construct a binary asynchronous counter: Clocked T- flip flops are used The output of one flip flop is connected to the clock input of next flip flop Input is applied to the clock input of first flip flop Output is taken from Q-outputs of all the flip flops together. 3/31/2013 Punjab Edusat Society (PES) 8 of 60

### PowerPoint Presentation:

J K Q A Ǭ J K Ǭ Q Input High Q B FFA FFB Initially both flip flops are reset i.e. Q A =Q B =0. This is state 0 of counter. Positive edge of first clock pulse causes Q A to go high. Flip flop B will not change state as Ǭ A has changed from high to low i.e. negative edge. Thus after first clock pulse Q A =1,Q B =0 3/31/2013 Punjab Edusat Society (PES) 9 of 60 1 1 =1 0 0 1

### PowerPoint Presentation:

Positive edge of second clock pulse causes Q A to go low. Flip flop B will also change state as Ǭ A has changed from low to high i.e. positive edge. Thus after second clock pulse Q A =0,Q B =1. 3/31/2013 Punjab Edusat Society (PES) 10 of 60 J K Q A Ǭ J K Ǭ Q Input High Q B FFA FFB 1 1 =0 1 1 0

### PowerPoint Presentation:

Positive edge of third clock pulse causes Q A to go high. Flip flop B will not change state as Ǭ A has changed from high to low i.e. negative edge. Thus after third clock pulse Q A =1,Q B =1 3/31/2013 Punjab Edusat Society (PES) 11 of 60 J K Q A Ǭ J K Ǭ Q Input High Q B FFA FFB 1 1 =1 0 1 0

### PowerPoint Presentation:

Positive edge of fourth clock pulse causes Q A to go low. Flip flop B will also change state as Ǭ A has changed from low to high i.e. positive edge. Thus after fourth clock pulse Q A =0,Q B =0. Which is same as starting state. 3/31/2013 Punjab Edusat Society (PES) 12 of 60 J K Q A Ǭ J K Ǭ Q Input High Q B FFA FFB 1 1 =0 1 0 0

### PowerPoint Presentation:

J K Q A Ǭ J K Ǭ Q Input High Q B Input 0 0 0 1 0 1 1 1 0 0 Q A Q B 3/31/2013 Punjab Edusat Society (PES) 13 of 60

### MOD-4 Counter:

MOD-4 Counter Clock Pulse Q B Q A Count 0 0 0 0 1 0 1 1 2 1 0 2 3 1 1 3 3/31/2013 Punjab Edusat Society (PES) 14 of 60

### PowerPoint Presentation:

J K Ǭ Q J K Ǭ Q J K Ǭ Q Q A Q B Q C High Input MOD-8 Counter 3/31/2013 Punjab Edusat Society (PES) 15 of 60

### PowerPoint Presentation:

0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 Input Q A Q B Q C 1 2 3 4 5 6 7 8 3/31/2013 Punjab Edusat Society (PES) 16 of 60

### PowerPoint Presentation:

Clock Input Q C Q B Q A Counter 0 0 0 0 0 1 0 0 1 1 2 0 1 0 2 3 0 1 1 3 4 1 0 0 4 5 1 0 1 5 6 1 1 0 6 7 1 1 1 7 3/31/2013 Punjab Edusat Society (PES) 17 of 60

### Divide by N Counter:

Divide by N Counter Sometimes for a particular digital system we may require to construct a counter having modulus of 3, 5, 7 or 9 i.e. modulus is not equal to 2 N . To design a counter with mod ‘k’ where k is less than 2 N . Then choose N such that 2 N-1 < k < 2 N Then N will be required number of flip flops. 3/31/2013 Punjab Edusat Society (PES) 18 of 60

### PowerPoint Presentation:

Then connect all the N flip flops as discussed in case of ripple counters. Determine which flip flops are in high state in final count e.g. in mod-10 counter (final count 1010) 2 nd and 4 th flip flops from left are in high state. Connect these outputs to a NAND gate and output of this NAND gate is connected to clear inputs of these respective flip flops. 3/31/2013 Punjab Edusat Society (PES) 19 of 60

### MOD-10 Ripple counter:

MOD-10 Ripple counter Q D Q C Q B Q A 0 0 0 0 1 0 0 1 1 0 1 0 0 0 Unstable State 3/31/2013 Punjab Edusat Society (PES) 20 of 60

### PowerPoint Presentation:

J K Ǭ Q J K Ǭ Q J K Ǭ Q J K Ǭ Q Q A Q B Q C Q D High Input 3/31/2013 Punjab Edusat Society (PES) MOD-10 Ripple counter 21 of 60

### PowerPoint Presentation:

MOD-12 Ripple counter Q D Q C Q B Q A 0 0 0 0 1 0 1 1 1 1 0 0 0 0 3/31/2013 Punjab Edusat Society (PES) 22 of 60

### PowerPoint Presentation:

J K Ǭ Q J K Ǭ Q J K Ǭ Q J K Ǭ Q Q A Q B Q C Q D High Input 3/31/2013 Punjab Edusat Society (PES) MOD-12 Ripple counter 23 of 60

### PowerPoint Presentation:

MOD-5 Ripple counter Q C Q B Q A 0 0 0 1 0 0 1 0 1 0 0 3/31/2013 Punjab Edusat Society (PES) 24 of 60

### Asynchronous Down Counter:

Asynchronous Down Counter C B A 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 3/31/2013 Punjab Edusat Society (PES) 25 of 60 Note that flip flop B changes state on positive edged transition of flip flop A and Note that flip flop C changes state on positive edged transition of flip flop B

### PowerPoint Presentation:

J K Ǭ Q J K Ǭ Q J K Ǭ Q Q A Q B Q C High Input Asynchronous Down Counter 3/31/2013 Punjab Edusat Society (PES) 26 of 60

### PowerPoint Presentation:

Asynchronous Down Counter 1 2 3 4 5 6 7 8 9 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 3/31/2013 Punjab Edusat Society (PES) 27 of 60

### Synchronous Counters:

Synchronous Counters Synchronous means driven by common clock input i.e. all flip flops change state at reference time of same clock (rising or trailing edge). Ripple counters have advantage of being simple but their speed is slow. (For example change of state from 111 to 000) 3/31/2013 Punjab Edusat Society (PES) 28 of 60

### Synchronous Counters:

Synchronous Counters The speed of operation improves significantly if all the flip flops are driven by same clock. The resulting circuit is known as synchronous counter. A single clock is applied to the clock input of all flip flops at the same time. 3/31/2013 Punjab Edusat Society (PES) 29 of 60

### Synchronous Counters:

Synchronous Counters Initially counter is RESET. At first clock Pulse as Q A is zero, flip flop B will not toggle. But flip flop A will toggle. Thus After first clock Q A =1 and Q B =0. J K Q A Ǭ J K Ǭ Q Clock Q B High A B 3/31/2013 Punjab Edusat Society (PES) 30 of 60

### PowerPoint Presentation:

Synchronous Counters At Second clock Pulse as Q A is high, flip flop B will toggle. Flip flop A will also toggle. Thus After second clock pulse Q A =0 and Q B =1. J K Q A Ǭ J K Ǭ Q Clock Q B High A B 3/31/2013 Punjab Edusat Society (PES) 31 of 60

### PowerPoint Presentation:

Synchronous Counters At third clock Pulse as Q A is zero, flip flop B will not toggle. But flip flop A will toggle. Thus After third clock Q A =1 and Q B =1. J K Q A Ǭ J K Ǭ Q Clock Q B High A B 3/31/2013 Punjab Edusat Society (PES) 32 of 60

### PowerPoint Presentation:

Synchronous Counters At first clock Pulse as Q A is high, flip flop B will toggle. Flip flop A will also toggle. Thus After first clock Q A =0 and Q B =0 (Starting State). J K Q A Ǭ J K Ǭ Q Clock Q B High A B 3/31/2013 Punjab Edusat Society (PES) 33 of 60

### PowerPoint Presentation:

Clock 0 0 0 1 0 1 1 1 0 0 Q A Q B Synchronous Counters 3/31/2013 Punjab Edusat Society (PES) 34 of 60

### Three Bit Synchronous Counter:

Three Bit Synchronous Counter Clock Q C Q B Q A 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 3/31/2013 Punjab Edusat Society (PES) 35 of 60

### PowerPoint Presentation:

J K Ǭ Q J K Ǭ Q J K Ǭ Q Q A Q B Q C High Clock 3-bit Synchronous Counter 3/31/2013 Punjab Edusat Society (PES) 36 of 60

Synchronous Decade Counter Clock D C B A 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 1 1 1 1 AB CD 00 01 11 10 00 01 11 10 For flip flop B 3/31/2013 Punjab Edusat Society (PES) 37 of 60

Synchronous Decade Counter Similarly by plotting K-maps for other flip-flops it can be shown that For flip flop C input will be equal to A.B For flip flop D input will be equal to A.B.C+ A.D For flip flop A input will be equal to 1 3/31/2013 Punjab Edusat Society (PES) 38 of 60

Synchronous Decade Counter 3/31/2013 Punjab Edusat Society (PES) 39 of 60

### Preset-able Counters:

Preset-able Counters Many Synchronous counters that are available as ICs are designed to be preset-able i.e. they can be preset to any desired starting count. This operation is also known as loading the counter. 3/31/2013 Punjab Edusat Society (PES) 40 of 60

### Preset-able Counter:

Preset-able Counter 3/31/2013 Punjab Edusat Society (PES) 41 of 60

### Procedure to Load desired Count:

Procedure to Load desired Count Apply the desired count to parallel data inputs P 0 , P 1 and P 2 . Apply a low pulse to Parallel Load input. This procedure will perform an asynchronous transfer of the P 0 , P 1 and P 2 levels into flip flops A, B and C respectively. 3/31/2013 Punjab Edusat Society (PES) 42 of 60

### Programmable Counters:

Programmable Counters In programmable counter circuit of preset-able counter is modified such that whenever counter reaches final count then initial programmed count is loaded instead of zeros. Consider following circuit 0 0 0 0 Parallel Load 3/31/2013 Punjab Edusat Society (PES) 43 of 60

### Ring Counters:

Ring Counters In a ring counter, the output of the last flip flop is connected back to the input of first flip flop. In the whole circuit only one flip-flop is set i.e. Q=1 at a time, all other flip-flops remain reset . On arrival of next clock pulse this 1 travels to next flip-flop. 3/31/2013 Punjab Edusat Society (PES) 44 of 60

### Ring Counters:

Ring Counters When last flip flop is set, then on arrival of next clock pulse the first flip-flop is set. In this manner 1 keeps on circulating in the register. Therefore it is called circulating register or ring counter. 3/31/2013 Punjab Edusat Society (PES) 45 of 60

### 4-bit Ring Counter:

4-bit Ring Counter D Ǭ Q Q A A D Ǭ Q Q B B D Ǭ Q Q C C D Ǭ Q Q D D Preset Clock Clear 3/31/2013 Punjab Edusat Society (PES) 46 of 60

### Ring Counter:

Ring Counter Initially flip-flop A is set with the help of ‘Preset’ input and all other flip-flops are reset with the help of ‘Clear’ inputs i.e. Q A =1 and Q B =Q C =Q D =0. As flip flops used are ‘D’ flip flops, therefore whatever input is applied will pass to output at next clock pulse and so on. 3/31/2013 Punjab Edusat Society (PES) 47 of 60

### Ring Counter:

Ring Counter Therefore after second clock pulse Q B =1 and Q A =Q C =Q D =0. Similarly on applying third clock pulse Q C =1 and Q A =Q B =Q D =0. Thus ‘1’ is shifted from first flip flop to last flip flop and again to the first flip flop with advancing clock. 3/31/2013 Punjab Edusat Society (PES) 48 of 60

### Ring Counter:

Ring Counter Clock Pulse Q A Q B Q C Q D Count 0 1 0 0 0 0 1 0 1 0 0 1 2 0 0 1 0 2 3 0 0 0 1 3 4 1 0 0 0 0 5 0 1 0 0 1 6 0 0 1 0 2 7 0 0 0 1 3 3/31/2013 Punjab Edusat Society (PES) 49 of 60

### PowerPoint Presentation:

Ring Counter Timing Diagram 1 2 3 4 5 6 7 8 9 Q A Q B Q C Q D 0 0 1 1 2 2 3 3 3/31/2013 Punjab Edusat Society (PES) 50 of 60

### Ring Counter:

Ring Counter The mod of Ring Counter is equal to the number of flip flops used in the counter. An n-bit ring counter can count only upto n-bits whereas an n-bit ripple counter can count 2 n states. 3/31/2013 Punjab Edusat Society (PES) 51 of 60

### Ring Counter:

Ring Counter So ring counter is uneconomical as compared to the ripple counter. But ring counter does not require any decoder since we can read the count by simply noting which flip-flop is set. Since it is entirely a synchronous operation and requires no external gates, therefore it is very fast. 3/31/2013 Punjab Edusat Society (PES) 52 of 60

### Twisted Ring Counter:

Twisted Ring Counter Also known as Johnson counter. In this counter inverted output of last flip-flop i.e. Ǭ is fed back to the input of first flip-flop instead of Q. All other connections are same as those of ring counter. 3/31/2013 Punjab Edusat Society (PES) 53 of 60

### Twisted Ring Counter:

Twisted Ring Counter D Ǭ Q Q A A D Ǭ Q Q B B D Ǭ Q Q C C D Ǭ Q Q D D Clock Clear 3/31/2013 Punjab Edusat Society (PES) 54 of 60

### Twisted Ring Counter:

Twisted Ring Counter Initially all the flip-flops are reset. At first clock input as Ǭ D =1, flip flop A will be set i.e. Q A =1. Q A will remain set till next three clock cycles when flip-flop D will be set. In this way each flip flop will remain set for 4 clock pulses and remain reset for another 4 clock pulses, thus generating total 8 states. 3/31/2013 Punjab Edusat Society (PES) 55 of 60

### Twisted Ring Counter:

Twisted Ring Counter 1 2 3 4 5 6 7 8 9 Q A Q B Q C Q D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clk 3/31/2013 Punjab Edusat Society (PES) 56 of 60

### Twisted Ring Counter:

Twisted Ring Counter Clock Q A Q B Q C Q D 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 8 0 0 0 0 9 1 0 0 0 3/31/2013 Punjab Edusat Society (PES) 57 of 60

### PowerPoint Presentation:

Twisted Ring Counter An n flip-flop twisted ring counter can count up to 2n pulses. So it is a mod-2n counter. It is more economical than normal ring counter. It requires two input gates for decoding regardless of the size of the counter. Thus it requires more decoding circuitry than normal ring counter but less than that of ripple counter. 3/31/2013 Punjab Edusat Society (PES) 58 of 60

### Ring Counters:

Ring Counters Both types of ring counters suffer from one common problem of lock-out i.e. if the counter finds itself in an unused state, it will persist in moving from one unused state to another forever. To rectify this problem additional gate has to be added to reset counter to a used state. 3/31/2013 Punjab Edusat Society (PES) 59 of 60

### PowerPoint Presentation:

3/31/2013 Punjab Edusat Society (PES) THANKS 60 of 60