# Arithmetic and Logic Circuits

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Category: Education

## Presentation Description

Introduction to Combinational, Sequential Circuits e.g. Adders, Subtractors, Animations.

## Presentation Transcript

### ARITHMETIC AND LIGIC CIRCUITS:

ARITHMETIC AND LIGIC CIRCUITS 2/11/2010 1 Punjab Edusat Society (PES) Subject: Digital Electronics, 3 rd Sem ECE Presented By: Kulwinder Singh Lecturer ECE Govt Polytechnic College for Girls, Ludhiana 97813-00151, kulwinderpannu@gmail.com

### Contents:

Contents Introduction Combinational, Sequential Circuits Half Adder Circuit with Animations Full Adder Circuit with Animations Half Subtractor Circuit with Animations Full Subtractor Circuit with Animations 4-bit Addition/ Subtraction IC 7483 2/11/2010 Punjab Edusat Society (PES) 2

### Introduction:

Introduction The digital computer is designed to perform arithmetic and logical operations using the operands in the binary form. To deal with such types of operations we can use two types of circuits: Combinational circuits. Sequential circuits. 2/11/2010 Punjab Edusat Society (PES) 3

### Combinational Circuits:

Combinational Circuits In combinational circuits the output at any given time is entirely dependent on the inputs which are present at that time. The binary values of output are functions of the binary combination of inputs at any given time. 2/11/2010 Punjab Edusat Society (PES) 4 Combinational circuit N input variables M output variables

### Combinational Circuits:

Combinational Circuits A combinational circuit can be represented by a truth table showing the binary relationship between N input Variables and M output variables. 2/11/2010 Punjab Edusat Society (PES) 5 1 2 3 …… N 1 2 …… M 0 0 0 …… 0 0/1 0/1 …… 0/1 1 1 1 ……. 1 0/1 0/1 ……. 0/1 I/Ps O/Ps

### Design of Combinational Circuits:

Design of Combinational Circuits To State the problem. Assignment of letter symbols to input and output variables. Construct the truth table that defines the relationship between inputs and outputs. Using the truth table express the result as boolean equation or K-map. Minimize and draw the logic diagram. 2/11/2010 Punjab Edusat Society (PES) 6

### Sequential Circuits:

Sequential Circuits In sequential circuits the output at any given time is not only dependent on the inputs which are present at that time but on the past values of the outputs. 2/11/2010 Punjab Edusat Society (PES) 7 Combinational circuit N input variables M output variables Memory

### Combinational V/S Sequential:

Combinational V/S Sequential Its output is determined by the present values of inputs only. It does not have a memory. It does not have a feedback. Its output is determined by the present as well as past values of inputs. It has a memory. It has feedback from output to input. 2/11/2010 Punjab Edusat Society (PES) 8

### Combinational V/S Sequential:

Combinational V/S Sequential Its operation can be described a truth table. It does not has a clock signal. Its circuit is simple. Its operation can be described a truth table and timing diagram. It may or may not has a clock signal. Its circuit is complex. 2/11/2010 Punjab Edusat Society (PES) 9

Adders Addition is one of the most important operation in digital arithmetic since it is also used in other arithmetic operations such as subtraction, multiplication, division, square root etc. In next slides we shall design adder and subtractor circuits to demonstrate the design of combinational circuits. 2/11/2010 Punjab Edusat Society (PES) 10

Half Adder A circuit which adds only two bits and produces one sum bit and one carry bit is known as half adder circuit. The name half adder stems from the fact that half adders are needed to implement full adders. 2/11/2010 Punjab Edusat Society (PES) 11

Naming Variables: Half adders There are two inputs bit1 and bit2, which are to be added, and two outputs sum and carry bits. Let us denote the inputs as A and B. Output sum as S and carry as C. 2/11/2010 Punjab Edusat Society (PES) 12

Truth Table: Half Adder A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 2/11/2010 Punjab Edusat Society (PES) 13

### K-Map for Variable ‘S’:

K-Map for Variable ‘S’ 1 1 2/11/2010 Punjab Edusat Society (PES) 14 0 1 0 1 A B S= A’B+AB’=A B

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 15 K-Map for Variable ‘C’ 1 0 1 0 1 A B C= AB

### Logic Diagram of Half Adder:

Logic Diagram of Half Adder 2/11/2010 Punjab Edusat Society (PES) 16 A B C S

Symbol of Half Adder 2/11/2010 Punjab Edusat Society (PES) 17 HA A B S C

Animation Half Adder AB=00 2/11/2010 Punjab Edusat Society (PES) 18 A B C= S= 0 0 0 0 0 0

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 19 Animation Half Adder AB=01 A B C= S= 0 1 0 0 1 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 20 Animation Half Adder AB=10 A B C= S= 1 0 0 1 0 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 21 Animation Half Adder AB=11 A B C= S= 1 1 1 1 1 1

FULL ADDER A full adder is a combinational circuit that forms arithmetic sum of three input bits. It consists of three inputs and two outputs. The two input variables X and Y represents the two significant bits to be added And third input Z represents the carry from the previous lower significant position. 2/11/2010 Punjab Edusat Society (PES) 22

Full Adder The outputs are designated by symbol S (for sum) and C (for carry). The binary variable S gives the value of least significant bit of sum The binary variable C gives the output carry. 2/11/2010 Punjab Edusat Society (PES) 23

Full Adder: Truth table X Y Z S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 2/11/2010 Punjab Edusat Society (PES) 24

### K-Map for Variable S:

K-Map for Variable S 1 1 1 1 2/11/2010 Punjab Edusat Society (PES) 25 00 01 11 10 0 1 XY Z S=X’Y’Z+X’YZ’+XY’Z’+XYZ =X YZ

### K-Map for variable C:

K-Map for variable C 2/11/2010 Punjab Edusat Society (PES) 26 1 1 1 1 00 01 11 10 0 1 XY Z C=XY+XZ+YZ

Logic Circuit Full Adder 2/11/2010 Punjab Edusat Society (PES) 27 X Y Z S C

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 28 Full Adder Using Half Adders Full Adder C in B C o (Carry out) Σ (Sum) Inputs Outputs Block Diagram Logic Diagram A B C o Σ Inputs Half Adder A A B C o Σ Half Adder Σ Outputs C in C o Full Adder

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 29 Animation Full Adder XYZ=000 X Y Z S= C= 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 30 Animation Full Adder XYZ=001 X Y Z S= C= 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 31 Animation Full Adder XYZ=010 X Y Z S= C= 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 0 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 32 Animation Full Adder XYZ=011 X Y Z S= C= 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 33 Animation Full Adder XYZ=100 X Y Z S= C= 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 34 Animation Full Adder XYZ=101 X Y Z S= C= 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 35 Animation Full Adder XYZ=110 X Y Z S= C= 1 1 0 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 2 3 4 5 6

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 36 Animation Full Adder XYZ=111 X Y Z S= C= 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 2 3 4 5 6

### Half Subtractor:

Half Subtractor A circuit which subtracts only two bits and produces one difference bit and one borrow bit is known as half subtractor circuit. The name half subtractor stems from the fact that half subtractors are needed to implement full subtractor . 2/11/2010 Punjab Edusat Society (PES) 37

### Naming Variables: Half subtractors:

Naming Variables: Half subtractors There are two inputs bit1 and bit2, and two outputs difference and borrow bits. Let us denote the inputs as X and Y. Output difference as D and borrow as B. 2/11/2010 Punjab Edusat Society (PES) 38

### Truth Table: Half Subtractor:

Truth Table: Half Subtractor X Y D B 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 2/11/2010 Punjab Edusat Society (PES) 39

### K-Map for Variable ‘D’:

K-Map for Variable ‘D’ 1 1 2/11/2010 Punjab Edusat Society (PES) 40 0 1 0 1 X Y D= X’Y+XY’=X Y

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 41 K-Map for Variable ‘B’ 1 0 1 0 1 X Y B= X’Y

### Logic Diagram of Half Subtractor:

Logic Diagram of Half Subtractor 2/11/2010 Punjab Edusat Society (PES) 42 X Y B D

### Symbol of Half Subtractor:

Symbol of Half Subtractor 2/11/2010 Punjab Edusat Society (PES) 43 HS X Y D B

### Animation Half Subtractor XY=00:

Animation Half Subtractor XY=00 2/11/2010 Punjab Edusat Society (PES) 44 X Y B= D= 0 0 0 0 1 0 0

### Animation Half Subtractor XY=01:

Animation Half Subtractor XY=01 2/11/2010 Punjab Edusat Society (PES) 45 X Y B= D= 0 1 0 1 1 1 1

### Animation Half Subtractor XY=10:

Animation Half Subtractor XY=10 2/11/2010 Punjab Edusat Society (PES) 46 X Y B= D= 1 0 1 0 0 0 1

### Animation Half Subtractor XY=11:

Animation Half Subtractor XY=11 2/11/2010 Punjab Edusat Society (PES) 47 X Y B= D= 1 1 1 1 0 0 0

### Full Subtractor:

Full Subtractor A full subtractor is a combinational circuit that forms arithmetic difference of three input bits. It consists of three inputs and two outputs. The two input variables X is minuend and Y is subtrahend. And third input Z represents borrow to the next lower significant position. 2/11/2010 Punjab Edusat Society (PES) 48

### Full Subtractor:

Full Subtractor The outputs are designated by symbol D (for difference) and B (for borrow). The binary variable D gives the value of least significant bit of difference The binary variable B gives the output borrow. 2/11/2010 Punjab Edusat Society (PES) 49

### Full Subtractor: Truth table:

Full Subtractor : Truth table X Y Z D B 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 2/11/2010 Punjab Edusat Society (PES) 50

### K-Map for Variable D:

K-Map for Variable D 1 1 1 1 2/11/2010 Punjab Edusat Society (PES) 51 00 01 11 10 0 1 XY Z D=X’Y’Z+X’YZ’+XY’Z’+XYZ =X YZ

### K-Map for variable B:

K-Map for variable B 2/11/2010 Punjab Edusat Society (PES) 52 1 1 1 1 00 01 11 10 0 1 XY Z B=X’Y+X’Z+YZ =X’(Y+Z) +YZ

### Logic Circuit Full Subtractor:

Logic Circuit Full Subtractor 2/11/2010 Punjab Edusat Society (PES) 53 X Y Z D B

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 54 Full Subtractors Full Subtractor B in B Inputs Outputs Block Diagram Logic Diagram A B Inputs Half Subtractor A A B Half Subtractor Outputs Full Subtractor B o (Borrow) D i (Difference) B o D i D i B o B o B in D i

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 55 Animation Full Subtractor XYZ=000 X Y Z D= B= 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 2 3 4 5 6 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 56 Animation Full Subtractor XYZ=001 X Y Z D= B= 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 2 3 4 5 6 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 57 Animation Full Subtractor XYZ=010 X Y Z D= B= 0 1 0 0 1 0 1 1 1 0 1 0 1 1 0 0 1 1 1 2 3 4 5 6 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 58 Animation Full Subtractor XYZ=011 X Y Z D= B= 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 2 3 4 5 6 1

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 59 Animation Full Subtractor XYZ=100 X Y Z D= B= 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 3 4 5 6 0

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 60 Animation Full Subtractor XYZ=101 X Y Z D= B= 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 2 3 4 5 6 0

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 61 Animation Full Subtractor XYZ=110 X Y Z D= B= 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 0

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 62 Animation Full Subtractor XYZ=111 X Y Z D= B= 1 1 1 1 1 1 0 1 1 1 0 1 0 0 1 0 1 1 1 2 3 4 5 6 0

4-Bit Addition 2/11/2010 Punjab Edusat Society (PES) 63 C 2 C 1 C 0 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 C 3 S 3 C 2 S 2 C 1 S 1 C 0 S 0

4-Bit Adder/ Subtractor Circuit 2/11/2010 Punjab Edusat Society (PES) 64 A B Y 0 0 0 0 1 1 1 0 1 1 1 0 Truth Table XOR Gate

### IC 7483 PIN Diagram:

IC 7483 PIN Diagram 2/11/2010 Punjab Edusat Society (PES) 65

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 66 IC Adders 8s 4s 2s Output Inputs Problem A 2 A 1 A 0 B 2 B 1 B 0 1s A 3 B 3 16s Σ 1 Σ 2 Σ 3 Σ 4 C 4 A 1 B 1 B 2 A 2 A 3 B 3 A 4 B 4 C 0 GND Vcc Carry input 7483 7483 4-bit binary adder

### PowerPoint Presentation:

2/11/2010 Punjab Edusat Society (PES) 67 THANKS