Zero-Delay Clock Buffers by IDT

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Presentation Description

Brief overview of IDT's zero-delay buffers. Zero-delay buffers (ZDB) are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.

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Presentation Transcript

Zero-Delay Buffers:

Zero-Delay Buffers IDT – World Leader in Timing Solutions Presented by Vik Chaudhry, Technical Marketing Manager at IDT

Zero Delay Buffers:

Zero Delay Buffers Zero Delay buffers are PLL-based buffers for zero propagation delay between input and output Supports various input and output styles Single-ended, differential and crystal (input only) Maximum output frequency 1GHz 8735I-21 8705I

Fanout Buffer Flyer:

Fanout Buffer Flyer

Applications Support :

Applications Support Prompt and effective customer support with technical issues. Simulation models, IBIS and HSPICE Layout and Schematics Review prior to tape out Evaluation boards Application notes Email Hotline: TSD-Applications@IDT.com OR clocks@idt.com

Thank You for Choosing IDT Timing Products!:

Thank You for Choosing IDT Timing Products!

Transcript:

Transcript Thank you for joining us for an overview of IDT's fanout buffers. My name Vik Chaudhry. I'm Marketing Manager for IDT's timing products. We also have zero delay buffers in our portfolio. A zero delay buffer is a PLL-based device that provides an output that is in phase alignment with the input signal. In this category of devices we have parts with multiple outputs, different levels of inputs and outputs, and different divider ratios. Designers like these types of devices when they want really tight control over timing of their board. IDT has a very large portfolio of fanout and clock distribution devices. To make it easy to select these parts, we have developed collateral that can be used. This collateral is located on the IDT website under clock and timing products. If you look under fanout buffers and dividers, you will see this collateral available. We also have an excellent application support for all the clocks and clock distribution devices. Most of our products include IBIS models. We also have application notes for various termination schemes, filter recommendations, and we also review schematics. If you have any questions, please feel free to either drop us an e-mail at tsd-applications@IDT.com or clocks@IDT.com . Thank you for choosing IDT timing products.

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