PCIe Clock Generators and Buffers: Ultra-low-power for PCIe Gen 1-2-3

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Presentation Description

The ultra-low-power IDT 9FGVxxxx (clock generators) and 9DBVxxxx (buffers) are the latest members of IDT's leading portfolio of PCI Express Gen1, Gen2 and Gen3 solutions, which also includes switches, bridges, signal repeaters, flash controllers and timing. The new PCIe timing devices consume less than 50 mW of power -- less than one-tenth the power required by previous solutions. The ultra-low power consumption reduces heat dissipation to ease cooling requirements in large-scale cloud computing applications. The new clock generators and buffers are available with a variety of termination options and features. Presented by Ron Wade, Technical Marketing Manager, Integrated Device Technology, Inc. For more information about IDT's PCI Express solutions, visit www.idt.com/go/PCIe.

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Ultra-Low-Power (ULP) Clocking Solutions for PCI Express Gen 1-2-3:

Ultra-Low-Power (ULP) Clocking Solutions for PCI Express Gen 1-2-3 IDT 9DBVxxxx and 9FGVxxxx August, 2012 Ron Wade Technical Marketing Manger Timing and Synchronization Division Ron.Wade@idt.com

PCI Express (PCIe) Clock Families:

PCI Express (PCIe) Clock Families Decreasing Power Consumption ULP LP

Ultra-Low-Power PCIe Clock Family:

Ultra-Low-Power PCIe Clock Family IDT’s PCI Express clocks consist of three main functions: Clock Generators or Synthesizers Clock Buffers (Fan Out and Zero-Delay) Clock Multiplexers (with and without integrated Fan Out) Here is the decoder for the ULP PCIe family: 9FGV are clock generators ( F requency G enerators) 9DBV are clock buffers ( D ifferential B uffers) 9DMV are clock multiplexers ( D ifferential M ultiplexers) V indicates 1.8V operation The first two digits after the V indicate the number of outputs – 02, 04, 06, 09, 10, etc. The 31 series have external terminations The 41 series have internal terminations with a Zo = 100 W The 51 series have internal terminations with a Zo = 85 W Devices with the same first 6 characters in the part number – 9FGV08xx are pin compatible with each other – so 9FGV0831/41/51 are pin compatible The 9FGV and 9DBV devices with the same number of outputs share the same pin out on the top, right and bottom of the device – the output side – and have only minor differences on the input side. Co-layout is possible and is fairly easy.

Ultra-Low-Power PCIe Gen1-2-3 Clocks:

Ultra-Low-Power PCIe Gen1-2-3 Clocks Buffers and clock generators Co-layout of buffers and clock generators is possible 1.8V Operation Absolute lowest power 2 to 8 Low-Power HCSL (LP-HCSL) outputs: Reduces IDDO from 15mA/output to ~5mA/output Reduces or eliminates termination resistors. Pin-selection or SMBus selection of key functions: PLL operating mode (clock buffers) Spread spectrum (clock generators) Selectable SMBus addresses on most devices Easy use of multiple devices without extra logic Status Pre-Production Availability Samples? Yes Production Sept. 30, 2012

Packaging & Typical Application Diagram:

Packaging & Typical Application Diagram Embedded/Communications Adapter Performance requirements are driving a transition from PCIe Gen 2 to Gen3 Board real estate is very tight due to growing functionality requirements Power densities continue to grow, causing increased thermal concerns Blue is package for new parts not including termination resistors (4x4, 5x5 and 6x6 mm^2) Yellow is package for old parts White number is number of outputs PCIe Switch CPU Chipset PCIe IO Ultra Low Power PCIe Clock Peripherals Memory PCIe IO Embedded/Communications Adapter

Key Applications:

Key Applications Cloud Computing/ Networking/Storage PCIe-based Solid State Drives Instrumentation - PXI Multifunction Printers Anywhere PCIe power/performance is a concern KEY APPLICATIONS

Ultra-Low-Power PCIe Key Benefits:

Ultra-Low-Power PCIe Key Benefits Ultra-Low-Power consumption Less than 1/10 th the power consumption of existing devices Ultra low operating costs Save $0.45 per year in energy costs per device* PCIe Gen1-2-3 support Design can be re-used through several generations Small form factor 4x4 to 6x6 mm packages High integration Optional integrated source terminations on LP-HCSL outputs Saves up to 16 resistors per device <1.5ps RMS phase jitter on REF output Suitable for 1Gigabit Ethernet applications * 1W costs $0.86/year in electrical/cooling in typical data center applications 9FG108 and 9FGV0831 8 o/p clock generators

Ultra-Low-Power PCIe Roadmap:

Ultra-Low-Power PCIe Roadmap

About the Ultra-Low-Power PCIe Family:

About the Ultra-Low-Power PCIe Family These devices are part of IDT’s PCIe Clocking Devices. All families offer PCIe Gen1-2-3 compliant devices. 557-xx 5V4106x 5V4123x 9FG 9DB 9ZX2 9FGL 9DBL 9ZXL 9FGV 9DBV Power Supply( ies ) 3.3V 3.3V 3.3V Core 1.05V-3.3V O/P 1.8V Core 1.05V-1.8V O/P Output Type HCSL HCSL LP- HCSL LP-HCSL # Outputs 1-4 4-19 4-19 2-8 (initially) REF output No Yes No Yes Pin Counts Packages 8-20 SOIC, TSSOP,QFN 28-72 TSSOP, QFN 20-72 QFN 24-48 QFN Term. Resistors (per Dif pair) 4 External 4 External 2 External or 0 External 2 External or 0 External Power (8 O/P Clock Gen) 412mW (4 O/P) 580mW 165mW 57mW ULP LP

9FGV Family Clock Generator Features:

9FGV Family Clock Generator Features

9DBV Family Buffer Features:

9DBV Family Buffer Features

Design Documentation:

Design Documentation Visit www.idt.com for additional information THANK YOU!

Transcript:

Transcript Hi, there. My name is Ron Wade, Technical Marketing Manager in the Timing and Synchronization Division of IDT. I'm going to give you a quick overview of our brand new ultra low power PCI Express Timing Solutions family. So, PCI Express can be thought of as having three generations of timing parts. The original technology was 3.3 volt HCSL output structure, which was developed in the early 2000's. For comparison sake here I'm taking an eight output clock generator from each technology. You can see that in this case the 3.3 volt HCSL which is the yellow and black burns 580 milliwatts of power to give you an eight output clock generator. In the mid 2000's, we developed a low-power HCSL output for use in notebook PC's, and normalizing to an eight output clock generator, that technology was able to provide a reduced power consumption of 165 milliwatts. What we're introducing today is an ultra low power PCI Express family and again, an eight output clock generator using the 9FGV or 9DBV devices which are the blue and white can give you that PCI Express Gen1, two, three clock generator for as little as 57 milliwatts. You can see that as we're decreasing the power here significantly we're also still providing you with the PCI Express Gen1 to Gen2 to Gen3 capability. So, the ultra low power PCI Express family consists of three main building blocks. There's the clock generators, there's the clock buffers, which are both fanout mode and zero delay, and the clock multiplexers, which have a single output or they have integrated fanout. The ultra low power PCI Express family part numbers all kind of play together and hang together and once you figure out the decoder ring, which is really simple here, you can kind of figure out what kind of part you need to plop into your design without any complicated selector guides. So, the FGV parts for the clock generators, FG stands for frequency generator. The DBV parts are the clock buffers. DV stands for differential buffer. The DMV parts are the clock multiplexers, which stands for differential multiplexers and the V indicates 1.8 volt operation. The first two digits are the V are the number of outputs, which currently range from two to eight, but will eventually range from one to ten. The 31 series parts have external terminations. The 41 series parts have a 100 ohm differential output termination and the 51 series parts have an 85 ohm output termination, to support the newer practices in PCI Express. So, devices with the first six characters in the part number say, 9FGV0831 or 41 or 51 are all compatible with each other except for that difference in the output terminations. For parts that have the same number of outputs whether it's a buffer or a clock generator, the output side of the part is identical between them. So, an 831 clock generator and a 831 buffer, the top, the right side and the bottom of the parts are all the same pin out which makes it easy to switch from one to the other in co-layout. So, the clocks as mentioned, the main functions are the buffers in the clock generators. These are 1.8 volt operation for the absolute lowest power consumption. We did do a lot of work to actually reduce the current required and these devices do actually draw less current than the yellow and the green technology parts that I'd mentioned previously. So, again, the outputs are two to eight today. They are low power HCSL which to the receiver looks exactly the same as the kind of legacy HCSL technology. The benefit here is that the current per output drops from 15 milliamps down to five and then we have the ability to integrate or have external the termination resistors. The other key thing we have is you may not have an SM bus handy and you don't need an SM bus to control the basic functions of the parts. The clock generator, for instance, there's a spread enable pin that enables you to have not only spread off, but to have a quarter percent down spread or half a percent down spread as a pin selection. Likewise, the buffers have a pin that allows you to select either high or low bandwidth or a bypass mode, which is a fanout with the PLL, as the name implies, bypassed and turned off. Also, the device that synthesizers have, two selectable SM bus addresses so that you can use up to two of them on the same segment. Most of the fanout buffers have three selectable SM bus addresses so that up to three of those devices can be used on the same SM bus segment and the buffers in the synthesizer addresses do not overlap. It's very easy to have up to five of these devices on the same segment without any external logic. All the parts are pre-production right now, samples are available now and will be in full production by the end of September.   A typical application for these is an embedded communications adapter where you've got a PCI Express switch, PCI Express IO, a CPU chip set or an FPGA and various peripherals in memory and performance requirements are from Gen1 to Gen2, going to Gen3. These parts cover the whole gambit of that performance envelope. The other thing in these types of applications as you cram more and more functionality in the same space as board real estate becomes very tight. Also, power densities continue to grow and as the power density grows, then thermal concerns tend to show up as well. So, these parts are available in commercial and industrial temperature ranges. They have a very low thermal profile and they are very small package-wise. Package comparison, not including the external termination resistors and not including the leads of the packages is shown here, where the original yellow parts are the T-SOP and SOIC-type packages. The blue boxes are the QFN's at the 9DBV and FGV parts come in. At the eight output level, a six by six millimeter QFN is significantly smaller than the original 48 pin T-SOP used by the eight output parts in the 3.3 volt HCSL range. Key applications, again, these parts are very much at home in cloud computing and in networking and storage. They're finding a very nice reception in PCI Express-based solid state drives due to their thermal characteristics, i.e. low power, pixie instrumentation, multi-function printers and basically anywhere where you need PC Express Gen1, 2, 3 with a very low power footprint. The key benefits of the ultra low power PCI Express or certainly the power consumption, it's less than one-tenth of the comparable function in the original 3.3 volt HCSL technology. Lower power consumption directly translates into lower operating cost. And using a benchmark of one watt cost 86 cents per year in a data center for not only the powering of the device, but the cooling of the device. Saving one watt saves 86 cents a year. So, going from an eight output yellow synthesizer to an eight output blue synthesizer results in 45 cents a year in reduced energy cost. These devices are PCI Express Gen1, 2, 3, which means that you can reuse the same device through multiple generations of your product. They're a small form factor. They're a four by four to six by six millimeters QFN's today. We will have a three by three for some of the very small parts in the near future. They have high integration. We have integrated output terminations for those environments where you're driving a homogeneous type of transmission line. In other words, all the transmissions lines are 100 ohm or 85 ohm. We also offer it without the internal terminations for cases where you may need to terminate to different types of loads. The ref on the synthesizers or the clock generators is a copy of the crystal and it is less than 1.5 picoseconds RMS phase jitter which means that it is suitable for gigabit Ethernet, which adds more integration capability to this device for your design. I'm not going to spend too much time on these slides. You can view these at your leisure. The clock generator family as it exists today, on August, 20, 2012 is shown here, where we segregate the number of outputs and basically allow you to pick your device based on your particular application requirements. Then likewise, the differential buffer family features are shown here where you've got the number of outputs, the number of OE pins, et cetera, end count, et cetera, et cetera, and schedule for the parts. In closing, I'd like to mention you can go to www.IDT.com for additional information and I would like to extend a very warm thank you for taking time to learn about IDT's ultra low power PCI Express Timing Solutions.

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