cmc2q06

Subcommittee on Standard MOS Varactor Model: 

Subcommittee on Standard MOS Varactor Model

Review of SP model provided by James Victory: 

Review of SP model provided by James Victory Features CV analysis including frequency dependence based on physics Distributed resistances Scalable with geometry Includes fringe terms between poly gate and well Includes temperature effects

Alterations to model that were discussed: 

Alterations to model that were discussed 1) The model was to include a third node to tie to either a diode for devices like NFET in Nwell representing the NW/SX parasitic diode or to tie to a fixed capacitor for SOI type devices. This node I think is already internal to the model, so we just need to make it an external node (bi). Agreed. 2) We proposed that the model be valid for a 'unit' device. The complete mosvar device is then a collection of these units wired in parallel. As such we do not need the number of fingers and number of gates in series instance parameters (nf and ns). The complete device is then represented using multiplicity. Agreed. See next page for picture of unit device. 3) There is currently a switch sw_res to calculate or not the various resistances I would propose to remove this switch as we want these in the model. We are going to keep this switch in the model. 4) The parameter rend_m(t) is to represent the metal to poly contact resistance. I think this should be considered as part of the metalisation that is being left out of this model. Agreed. 5) A parameter and calculation is needed for the vertical resistance through the poly from the silicided portion down to the gate itself. Rvertg / (Wg * Lg) This term is much bigger than the resistance along the silicided portion and so the combined effect results in simply adding this term to the other. We are going to add this term using the parameter name 'rpv'.

Unit Cell of MOS Varactor: 

Unit Cell of MOS Varactor

Alterations to model to be discussed (2): 

Alterations to model to be discussed (2) 6) The distributed resistance parameters (dgp0 and dsp0) are now set to 3. Is there ever a case where these would not be 3? Should we fix these values rather than have them as model parameters? These parameters will be fixed to 3. 7) There is an adjustment (reduction) to the well resistance under the gate due to the charge that is built up in accumulation. We have also observed in our devices an increase in the well resistance in the depletion region that presumably is the result of the depletion region effectively narrowing the cross section for carriers to move laterally under the gate. (The same effect is observed in diffusion resistors.) This effect is not included in the model. Is it something we do want to include at this point? There was some discussion as to the root cause (a reduction in cross section versus a difference in doping levels). I asked that those who are willing to share any data that they may have on this effect to please forward it to me. 'Thanks!,' in advance. We generally believed that this effect should be included in the model. 8) Gate leakage is not yet included in the model. In the initial model I sent out, this was easily handled by adding a term at the point where the ddt operator is invoked. So, once we settle on an expression to calculate the leakage current, getting this into the model will be very easy. This was to be included in the newest PSP version but is not. We need to get this into the model. I will add a simple expression for use in beta checking.

Other Issues: 

Other Issues I have not had time to think about the details of how we can make this model usable within differential varactors (Philips and IBM request). This is an important issue and still needs to be addressed. We had a request from our Intersil colleagues to include Dit terms to account for fast interface states resulting from high radiation environments. Someone mentioned that this is already in the model, but I do not think that this is the case. So, we should probably discuss whether this feature will be included in V1.00 or a later version. This effect is also already in the PSP version and so should be included in the initial release. Like the FET model, this model uses Tox as a model parameter. I would prefer to use Cox as there are already many values of Tox, (optically measured, one measured from capacitance, and one measured from leakage). Further, gate oxides are not the homogeneous materials they might have once been, but are now layers of different types of oxides, presumably with different dielectric constants. The Tox value now is really an average weighted by the choice of dielectric constant. I'd rather be honest up front and say there is some Cox that is the result of various things and not try to break this down to fundamental quantities for which we use 'effective' values. We do want to remain common with the FET model in terms of parameters and I am guessing that the FET guys will not want to change. That certainly outweighs my semantic concerns. Not going to happen. Inclusion of non-constant doping profile in the well as one moves away from the oxide. Again, is this to be included here in V1.00 or in a later version? See discussion on next page.

Effects of Variation in Doping Profile: 

Effects of Variation in Doping Profile There is an upturn in capacitance as one goes deeper into depletion. This is unaccounted for in original PS model, but can now be handled by a voltage dependent effective doping level. The original IBM proposed model did treat this with minr parameter that was 'due to some holes being around.' There is certainly a non-constant doping profile under the gate as shown by SIMS, though absolute values are in question. These variations will certainly have an effect on the CV curves. How much of this upturn is due to the time it takes to make the measurement and the onset of inversion from thermal creation of holes? Increasing the integration time in our measurements shows a slightly enhanced upturn in the capacitance. Is the rest due to doping variations or something else? Need a more physical methodology than either of the two methods used so far. Both are little more than curve fits. Solution will take time. Do we use a curve fit at this time in order to get a model out for testing and promise to fix this in a future release, or do we take the time now to study this issue and satisfactorily resolve it?

Next Steps: 

Next Steps Send out these meeting results to everyone. James has just sent (6/19) Ted a copy of PSP implementation. Ted will come to some kind of understanding of the model and make any fixes as we have outlined in these discussions. This has been delayed due to work commitments. Further testing of model is needed for cases like pMOS varactors and P-gates over Nwell. Try to have a Beta version to release to everyone in late-July for testing. Monthly phone meetings to get results and make any alterations, the idea being to have a discussion of these results at the next meeting. Documentation needs to be addressed QA document for testing Model details document Put documents on website when they are more finalised. Define role of university support. Genady seems to be the logical choice for this since this model is so closely related to the new PSP FET model. What do we expect of him in this role? Amount of compensation?