AJ EuroSoC

Slide1: 

EuroSoC Towards a Joint University/Industry Research Infrastructure for System on Chip & System in Package 20th February 2004

EuroSoC Meeting20th February 2004, Paris, France: 

10h00 EuroSoC global presentation Trends New format: Joint Academia/Industry Infrastructure Charter Interim activity programme Open Q&A 10h30 Industrial perspectives to open research issues Semiconductor point of view, Philippe MAGARSHACK, STMicroelectronics System house point of view, Klaus KRONLÖF, Nokia 11h30 Design activities funding trends SoC funding in the MEDEA+ Programme, Alexander SEDLMEIER, MEDEA+ Office SoC funding in the FP6 Programme, Philippe REYNAERT, EC 12h30 Open discussion: Will there be any design activity left in Europe after 2008? 13h00 End of Plenary meeting 13h00 Parallel Thematic workshops EuroSoC Meeting 20th February 2004, Paris, France

Outline: 

Outline SoC design trends and Paradigm shifts EuroSoC Status New format: Joint Academia/Industry Infrastructure Interim activity programme Open Q&A

SoC Design Strategic Issues (Handel Jones): 

SoC Design Strategic Issues (Handel Jones) IC VENDORS THAT ARE STRONG IN DESIGN ARE GENERALLY THE MOST PROFITABLES AND ARE IN SUPERIOR MARKET POSITION DESIGN STRENGTHS INCLUDE COMBINATION OF DESIGN TOOLS USED, TRAINING OF ENGINEERES, IP PORTFOLIO, AND LINKING WITH PROCESS PARAMETERS DATA SHOWS STRONG CORRELATION BETWEEN DESIGN STRENGTHS AND PROFITS IMPACT OF DESIGN STRENGTH MAY LAST MANY YEARS, 5-7 YEARS FOR MARKET POSITIONNING DESIG PROBLEMS ARE BECOMING MORE SEVERE AS FEATURE DIMENSIONS DECREASE

ASIC is dead, the future is SoC Design, from Wires to Higher level interconnect: 

ASIC is dead, the future is SoC Design, from Wires to Higher level interconnect Adapted from F. Schirrmeister (Cadence Design Systems Inc.) 1970’s 1980’s 1990’s abstract abstract cluster abstract cluster RTL Transistor model (t=RC) Gate level model 1/0/X/U (D ns) Register-transfer level model data[1011011] (critical path latency) 2000’s 2010+ CPU How to abstract HW-SW Interfaces? Physical effects How to compose Heterogeneous components

Paradigm Shift: 

Paradigm Shift Application changes, designers hard to scale Computation models, CPUs, network and massive memory on chip Smart devices, Analog/RF and MEMS on chip Technology advances, methods and tools don’t scale Nano technologies, Need to rethink backend Multi-physics issues Design methods, need to rethink front-end Platformization of competitive applications Low cost high performance new smart SoC design Detecting breakthroughs, corporate R&D are no more adapted Long-term funds and attention Pluridisciplinarity requires research in too many directions.

Long Term Research Funding Issues: 

Long Term Research Funding Issues Falling of the “Bell Labs” model Need ROI proof New cost model required for long-term research Emerging schemes USA: University/Industry Research Labs (Intel, Microsoft), Networks (CITRIS), foundations (SRC) Asia Pacific: industry funded nationally coordinated research (Taiwan, Korea, China, Japan) Europe: Medea+ (Coordinated by industry), EC Future: University/Industry Collaborative long-term Research

SRC: Semiconductor Research Corporation: 

SRC: Semiconductor Research Corporation Goals: define common industry needs, invest in and manage the research that would expand the industry knowledge base and attract premier students to study semiconductor technology. Benefit: Operates globally to provide competitive advantage to its member companies Model: SRC plans and manages a program of basic and applied university research on behalf of its participating members. Actions since 1982: funded more than $500 million in long-term semiconductor research contracts.

How to make it happen in Europe ?: 

How to make it happen in Europe ? Show importance of European advances in SoC design DATE, SoC Conference, MPSoC Show importance of SoC design for European Industry Success stories, Leadership in MM, Automotive Have best students working on SoC design Better training and carrier opportunities Create a European long term vision to realign research Pluridisciplinary roadmaps Ensure enough funding Proactive SoC community: ASIC is dead (GO) SoC, NoC, MPSoC, Application specific platform

Outline: 

Outline SoC design trends and Paradigm shifts EuroSoC Status New format: Joint Academia/Industry Infrastructure Interim activity programme Open Q&A

Identification of Research Areas and Actors: 

Identification of Research Areas and Actors Sophisticated 2 Years’ process Step 1: Detect all SoC competencies in different countries Build geographical sub-networks Joint University/Industry leadership Step 2: Detect key actors in different SoC thematic areas Existing specialized networks Existing European projects Step 3: Identify key research areas Key nodes (research institute + industrial partner) Identify potential contributors (from university and industry) 1000+ Researchers, 160 institutions, 100++ institutions

Key Areas, Key Academia Contibutors: 

Key Areas, Key Academia Contibutors Multi-physic, Marta RENCZ, Univ. of Budapest, Hungary Quality and test, Christian LANDRAULTLIRMM, F Mixed Signals, José L. HUERTAS Univ. of Sevilla, S Low Power, Christian PIGUETCESM SA, Switzerland Network-on-ship, Hannu TENHUNEN, KTH, Sweden System timing, Mark JOSEPHS, SBU, UK Reconfigurable Systems, Tughrul ARSLAN, ISLI, UK Hardware-dependent Software, Rolf ENRST, UBR, D Integrated Intelligence, Patrick DEWILDE, DUT, NL System modelling, Alain VACHOUX, EPFL, Switzerland IP re-useAlain GREINER, UPMC, F Verification, Dominique BORRIONE, TIMA laboratory, F Mmethodologies and flows, Francky CATTHOOR, IMEC, B SoC Applications, Norbert WHEN, Univ Kaiserlautern, D Luciano LAVAGNO, Polit. di Torino, I

EuroSoC Contributors: 

EuroSoC Contributors

Outline: 

Outline SoC design trends and Paradigm shifts EuroSoC Status New format: Joint Academia/Industry Infrastructure Interim activity programme Open Q&A

The Charter: 

The Charter To build a joint academia/industry infrastructure allowing to increase the effectiveness of European research and then to reduce the cost of industrial R&D. Complement existing organisations aimed to coordinate industrial practices to address long term pluridisciplinary research areas related to SoC. Help European industry to outsource its long term R&D and to facilitate the access to academic research environment for greater contribution to industrial R&D.

EuroSoC New Format: 

EuroSoC New Format Joint Academia/Industry Research Infrastructure Long-term Collaborative Research Industry can steer European long term research Share cost of long term research Steps: 2004 2005 2007 Help researchers to get additional funding and get additional Funding for infrastructure to Cover all areas Start with Existing funding and amodest income to build an office, project database and a modest research programme Joint Infrastructure Fully Operational to Coordinate and realign European efforts

Long Term Workprogramme: 

Long Term Workprogramme Systematic process to detect breakthroughs and to realign full European education and research Pluridisciplinary Roadmapping & standardization (conceptualization and interfaces between disciplines) Build a pluridisciplinary education Driving Applications : Ambiant intelligence

Outline: 

Outline SoC design trends and Paradigm shifts EuroSoC Status New format: Joint Academia/Industry Infrastructure Interim activity programme Open Q&A

Projects Database: 

Projects Database List of Grants and funds perceived by contributors (Industrial, national and European funds) List of main application domains covered by the research of contributors List of spectacular success stories where contributors participated (e.g. flying insect robot) List of events where contributors are key organizers. Goals Show importance of SoC design activities Increase awareness of contributors Build synergy between projects Ease interaction between contributors Effective partnership Identification of umbrella projects

Initial Working Programme: 

Initial Working Programme Starting with a restricted scope, Network-on-Chip (NoC). Quite a large number of national funded activities. The NoC activity is supposed to serve as a demonstrator for the other thematic areas. Activities have been identified for the NoC area: Roadmapping Education and continued training Coordination of national and European R&D projects Conferences (SoC, NoC, MPSoC) Gradual extension to other thematic area according to industrial support Additional funding required to coordinate running activities

Conclusion: 

Conclusion ASIC is dead, the future is SoC Design Long term research no more affordable for single players, even Intel Federate and restructure European long term research to create the pluridisciplinarity required to cope with evolution of applications and technologies. Joint Academia/Industry infrastructure to empower integrated system innovation process.

Open Q&A: 

Open Q&A

FAQs: 

FAQs EuroSoC is too broad SoC require pluridisciplinarity Added value compared to DATE Proactivity and research realignment Too many partners Long term research requires two level critical mass Additional added value compared to European projects Longer term and pluridisciplinary objectives No EDA in Europe Next generation EDA is European so far

Your Questions: 

Your Questions

Thank You: 

Thank You