Slide1 : Futures for DSM Physical Implementation: Where is the Value, and Who Will Pay? Andrew B. Kahng
abk@cs.ucla.edu , http://vlsicad.cs.ucla.edu
UCLA Computer Science Department
12th DA Show, Tokyo
July 14, 2000
Subwavelength Optical Lithography : Subwavelength Gap since .35 m Subwavelength Optical Lithography Numerical Technologies, Inc.
“The Design Productivity Gap” : “The Design Productivity Gap” Equivalent Added Complexity 68 %/Yr compounded
Complexity growth rate 21 %/Yr compound
Productivity growth rate Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design 250 nm 13 M Tr. 400 MHz 210 90 M
250 nm 20 M Tr. 500 270 120 M
180 nm 32 M Tr. 600 360 160 M
2002 130 nm 130 M Tr. 800 800 360 M * @ $ 150 k / Staff Yr. (In 1997 Dollars) Logic Tr./Chip
Tr./S.M. “How many gates
can I get for $N?” Source: SEMATECH Potential Design Complexity and Designer Productivity
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
What is design closure? : What is design closure? “front end consistent
with back end” meet constraints here
Û
meet constraints there What is the problem ? source: K. Keutzer, DAC 2000
Slide8 : Design closure == predicting interconnect
Aristo, DAC-2000 panel : Aristo, DAC-2000 panel
Gate-Level Place & Route
Gate-Level Optimization Design
Constraints IP Blocks Library
Top-Level Routing
RC Extraction
Timing Analysis Early Planning Design Refinement Chip Assembly PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE TYPICAL DESIGN FLOW Design
Netlist Gate-Level
Verilog Concurrent Block Partitioning, Clustering & Placement “Olympic Flame”
Slide10 : Physical Prototyping Design Signoff Monterey, DAC-2000 panel “Recycle Bin”
Slide11 : Sequence Place & Route Prepare Database 3D Extraction True-3D Parasitics Delay Calculation Timing Analysis Timing Analysis Interconnect Driven Optimization Interconnect Driven Optimization Synthesis RTL Timing Sign-off Driver sizing, topology-based optimization Sequence, DAC-2000 panel “Anakin Skywalker’s Pod Racer”
Clear Thinking: Basics of Design Convergence : Clear Thinking: Basics of Design Convergence What must converge ?
logic, timing, and spatial embedding
support front-end signoff, provide predictable back-end
Ways to achieve Convergence through Predictability
correct by construction (“assume, then enforce”)
constraints and assumptions passed downstream; not much goes upstream
ignores concerns via guardbanding
separates concerns as able (e.g., FE logic/timing vs. BE spatial embedding)
construct by correction (“tight loops”)
logic-layout unification; synthesis-analysis unification, concurrent optimization
elimination of concerns
reduced degrees of freedom, pre-emptive design techniques
e.g., power distribution, layer assignment / repeater rules, GALS/LIS
What Must A Design Closure Tool Look Like ? : What Must A Design Closure Tool Look Like ? Input
RT-level HDL + technology + constraints
Output
“go”: recipe for invocation and composition of “commodity” SP&R
“no go”: diagnosis of RTL code problems
Logical and physical hierarchies co-evolve
spatial: top-down coarse placement physical hierarchy
logic/timing: implementable RTL logical hierarchy
limits of human fanout, organizations always have hierarchy
natural sequence of no-floorplanning, phys-floorplanning, RTL-floorplanning...
Details (must construct, predict, ignore, eliminate, ...)
pin optimizations, interconnect planning, hierarchy reconciliations, budgeting mechanisms, compatibility with downstream SP&R, ...
DON’T Develop This RTL Planning Technology : DON’T Develop This RTL Planning Technology Don’t spend too much time packing blocks that will change
goal = early diagnosis, or handoff to commodity SP&R
pre-synthesis uncertainty = +/- 15% area, timing
wirelength, path timing ® must be connectivity-centric, not packing-centric
easier to work on direct realizations of the floorplan, not representations
need relative coarse placement that adapts to incremental ECOs
Don’t over-constrain block shaping (rectangles, L’s, T’s)
placers handle constraints w/ granularity = site spacing, row height
constructive pin assignment ® don’t need roundness
path timing optimization ® may even want disconnected shapes
Don’t under-constrain layout region
fixed-die planning: simultaneous zero-whitespace, zero-overlap
Do Allow the Following... : Do Allow the Following... 1.0 1.0 0.5,0.5 Blk A Blk B
It Is What the Cells Want Anyway ! : It Is What the Cells Want Anyway !
Do Develop This RTL Planning Technology : Do Develop This RTL Planning Technology RTL partitioning
understand interaction b/w block definition and placement quality
recognize and cure a physically challenged logic hierarchy
Global interconnect planning and optimization
symbolic route representations to support block plan ECOs
Controllable SP&R back end (including power/clock/scan)
Incremental / ECO optimizations, and optimizations that are “robust” under partial or imperfect design knowledge
Better estimators (“initial WLMs”)
to account for resource, topological heterogeneity
to account for optimizations (placement, ripup/reroute, timing)
“earliest RTL signoff with detailed P&R knowledge”
Conclusion : Conclusion RTL-to-GDSII will commoditize SP&R market sectors
Many solutions are reasonable and will survive in the marketplace RTL-down SP&R becomes a “commodity”
No solution is complete
Key missing pieces include RTL partitioning; hierarchy and block management; real working RTL diagnosis and signoff
Individual point technologies (e.g., global placement or detailed routing) become less valuable integration is most important
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
Subwavelength Optical Lithography : Subwavelength Gap since .35 m Subwavelength Optical Lithography Numerical Technologies, Inc.
Optical Proximity Correction (OPC) : Optical Proximity Correction (OPC) Corrective modifications to improve process control
improve yield (process window)
improve device performance
Future OPC-Related Technologies : Future OPC-Related Technologies WYSIWYG broken ® (mask) verification bottleneck
Function-aware OPC insertion
OPC insertion is for predictable circuit performance, function
tool understands functional intent, makes only the corrections that win $$$, reduce performance variation
applies to mask inspection as well
OPC- and manufacturing-aware layout
don’t make corrections that can’t be manufactured or verified
model effects of geometry on OPC cost needed to yield function
understand (data volume, verification) costs of breaking hierarchy
Difficult solutions to flow issues
e.g., how to avoid making same corrections 3x (library, router, PV)
Phase Shifting Masks (PSM) : Phase Shifting Masks (PSM)
Double-Exposure Bright-Field Alternating PSM : Double-Exposure Bright-Field Alternating PSM 0 180 180 + = Positive photoresists for poly, metal unexposed areas = printed features
Why is Alternating PSM Valuable and Essential ? : Why is Alternating PSM Valuable and Essential ? PSM enables smaller transistor gate lengths Leff
“critical” polysilicon features only (gate Leff)
faster device switching ® faster circuits
better critical dimension (CD) control ® better parametric yield, $/wafer
Full-chip PSM (poly, local interconnect) denser layouts
smaller die area ® more $/wafer
achieving Roadmap for device density depends on PSM
Data points
25 nm gates manufactured with 248nm DUV steppers (NTI + MIT Lincoln Labs, June 2000)
90nm gates in production at Motorola, Lucent since 1999
Alternative: $5 B fab with equipment that doesn’t exist yet
The Phase Assignment Problem : The Phase Assignment Problem Assign 0, 180 phase regions such that critical features with width < B are induced by adjacent phase regions with opposite phases 0 180
Key: Global 2-Colorability : Key: Global 2-Colorability ? 180 0 0 180 180 180 Odd cycle of “phase implications” ® layout cannot be manufactured
layout verification becomes a global, not local, issue
Slide28 : F4 F2 F3 F1 Critical features: F1,F2,F3,F4
Slide29 : F4 F2 F3 F1 Opposite-Phase Shifters (0,180)
Slide30 : F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7 S8 Shifters: S1-S8 PROPER Phase Assignment:
Opposite phases for opposite shifters
Same phase for overlapping shifters
Slide31 : F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7 S8 Phase Conflict Proper Phase Assignment is IMPOSSIBLE
Slide32 : F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7 S8 Phase Conflict feature shifting
to remove overlap Phase Conflict Resolution
Slide33 : F4 F2 F1 S1 S2 S3 S4 S7 S8 Phase Conflict feature widening to turn
conflict into non-conflict Phase Conflict Resolution F3
Future PSM-Related Technologies : Future PSM-Related Technologies UCLA-Cadence: first comprehensive methodology for AltPSM layout design
3-way shared responsibility for phase-assignability
good layout practices (local geometry)
no T shapes, no doglegs, even-length transistor fingers, ...
but no complete set of “rules” exists
automatic phase conflict resolution (global 2-colorability)
latest technology: optimal conflict resolution for 50K polygons in 6 sec
reuse of layout (free composability)
problem: guarantee reusability of phase-assigned layouts, such that no odd cycles can occur when the layouts are composed together in a larger layout
Changes all flows: library design, custom design, SP&R
Macroscopic Process Effects : Macroscopic Process Effects CMP, SOG RIE CVD Dummy Fill controls several types of process distortions : R. Pack, Cadence
Field-Dependent Aberration : Field-Dependent Aberration Field-dependent aberrations cause placement errors and distortions
R. Pack, Cadence
Conclusions : Conclusions RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Closely related to foundry capital expenditure
Unites EDA with much of mask industry, even process development
Expands scope of physical “verifications”, moves awareness upstream into “syntheses” (logic, layout)
Very comprehensive changes to data model, infrastructure, flows
Unified, front-to-back solutions will win
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
The Productivity Gap : The Productivity Gap Equivalent Added Complexity 68 %/Yr compounded
Complexity growth rate 21 %/Yr compound
Productivity growth rate Year Technology Chip Complexity Frequency Staff Staff Cost* 3 Yr. Design 250 nm 13 M Tr. 400 MHz 210 90 M
250 nm 20 M Tr. 500 270 120 M
180 nm 32 M Tr. 600 360 160 M
2002 130 nm 130 M Tr. 800 800 360 M * @ $ 150 k / Staff Yr. (In 1997 Dollars) Logic Tr./Chip
Tr./S.M. “How many gates
can I get for $N?” Source: SEMATECH Potential Design Complexity and Designer Productivity
Mask Cost : Mask Cost But: average only 500 wafers per mask set !
“Keep the Fabs Full” : “Keep the Fabs Full” Design technology must keep manufacturing facilities fully utilized with:
high-volume parts
high-margin parts
Foundry capital cost > $2B
How much value of new designs is needed to fill the fab ???
Design Productivity Need + DSM = 2 EDA Trends : Design Productivity Need + DSM = 2 EDA Trends source: MARCO GSRC
Fab Amortization Close the Implementation Gap : Fab Amortization Close the Implementation Gap Effort/Value Level of Abstraction source: MARCO GSRC
Slide44 : Percent of die area that must be occupied by memory to
maintain SOC design productivity Design Productivity Gap Low-Value Designs? Source = Japanese system-LSI industry
Reduce Back-End Effort ? : Reduce Back-End Effort ? Example: repeating dense wiring fabric
pattern at minimum pitch - Eliminates signal integrity, delay uncertainty concerns
- But has at least 60% - 80% density cost source: MARCO GSRC
Improve IP Reuse Productivity ? : Improve IP Reuse Productivity ? source: MARCO GSRC
QUALITY Problem : > 1000x Energy-Flexibility Gap : Embedded mProcessors LP ARM
0.5-2 MIPS/mW ASIPs
DSPs 1 V DSP
3 MOPS/mW QUALITY Problem : > 1000x Energy-Flexibility Gap Dedicated
HW Flexibility (Coverage) Energy Efficiency
MOPS/mW (or MIPS/mW) 0.1 1 10 100 1000 Reconfigurable Processor/Logic
10-50 MOPS/mW
100-200 MOPS/mW Source: Prof. Jan Rabaey, UC Berkeley
“Keep the Fabs Full” : “Keep the Fabs Full” Design technology must keep manufacturing facilities fully utilized with:
high-volume parts
high-margin parts
What happens when design technology “fails” ?
not enough high-value designs
the semiconductor industry will find a “workaround”
reconfigurable logic
platform-based design
Platform-Based Design : Platform-Based Design source: MARCO GSRC
Conclusions : Conclusions RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality ASIC business model is at risk
TAT achieved at cost of QOR
low QOR low silicon value
electronics industry chooses reprogrammable, platform-based “workarounds”
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
EDA Industry Structure: Vendor Side : EDA Industry Structure: Vendor Side Tool usage focus still the core of the business model
slows down the move to open systems, open infrastructure
Some indicators of “immaturity”
lack of metrics and other common infrastructure
LEF/DEF, SPEF, *SPF, OLA, .lib, ... are a minimal start, were slow to develop
no differentiation between strategic, commodity technology
Some indicators of “poor health”
customer integration investment is 2.5x - 4x times tool investment
EDA R&D » 20% of revenue, but 80+% of R&D = support, infrax
R&D often provided by customers (designers), outsourced (M&A)
EDA Industry Structure: Customer Side : Collectively, insist that EDA be “everything to everyone”
fragmentation of vendor R&D resource, lots of secret options, ...
tools attempt to fit in all methodologies ® fit in none
Won’t let EDA vendors evolve to a more sustainable model
push for low ASPs while spending 4x on integration ® low R&D levels
sometimes invest in fragmentation of R&D talent (20 SP&R, 70 verif startups)
No differentiation between strategic, commodity technology
one-offs, hidden options
very little cooperative foundation: e.g., data model + API, silicon calibration, library char, RLC extraction, gate/int delay calc, STA, physical verification EDA Industry Structure: Customer Side
Must Escape “Death Spiral” : “Failure of EDA”
® why pay for it
® why invest in it
® why work on it
® ...
Must stop wasting scarcest of all resources: brains
how many GDSII parsers do we need ? how many interconnect delay calculators ? how many netlist connectivity data models ?
acknowledge de facto commodity technology
turn these technologies into common infrastructure
Mature behavior is required
with respect to “strategic vs. commodity” distinction
with respect to “control” Must Escape “Death Spiral”
Conclusions : Conclusions RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality
EDA industry must evolve and mature to achieve EDA industry productivity
eliminate wastage on duplicated commodity infrastructure
acknowledge and share de facto commodity technologies
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
CAD Life Cycle Questions : CAD Life Cycle Questions What will the design problem look like?
How can we quickly develop the right design technology?
Did I really solve the problem?
Did the design process improve?
Did achievable design envelope get bigger?
Proposal: We MUST develop shared infrastructure to answer all three questions
1. Technology Extrapolation : 1. Technology Extrapolation Evaluates impact of
design technology
process technology
Evaluates impact on
achievable design
associated design problems
Questions to be addressed:
What will the design problem look like ?
Sets requirements for CAD tools, methodologies, investment
Familiar example: ROADMAPS How and when do L, SOI, SER, etc. matter? What is the most power-efficient noise management strategy? Will layout tools need to perform process simulation to effectively model cross-die and cross-wafer manufacturing variation?
Optimal Repeater Sizing : Most commonly used optimal repeater sizing expression (Bakoglu)
New study:
Sweep repeater size for single stage in the chain
Examine both delay and energy-delay product
Optimal Repeater Sizing
Slide60 : Cu Resistivity: Effect of Line Width Scaling Effect of Electron Scattering Effect of 5 nm Barrier Conformal 5 nm barrier assumed
Even a 5 nm barrier will increase resistivity drastically No barrier assumed
Electron scattering increases resistivity
Lowering temperature has a big effect 525
320
250 95
58
48 280
170
133 ITRS 1999 Line width (nm) Global
Semiglobal
Local source: MARCO IFRC
Slide61 : Cu Resistivity: Barriers Deposition Technology Atomic Layer Deposition (ALD)
Ionized PVD
Collimated PVD 5 nm barrier assumed at the thinnest spot
No scattering assumed, I.e., bulk resistivity Interconnect dimensions scaled according to ITRS 1999 source: MARCO IFRC
What Technology Extrapolation is Available Today? : What Technology Extrapolation is Available Today? Too many Roadmaps
ITRS, JISSO, STARC, … Roadmaps
some university tools: SUSPENS, GENESYS, RIPE, BACPAC, …
numerous tools in industry
Observations
everyone predicts “same” parameters but different assumptions, inputs: near-total duplication of effort !!!
no documentation or visibility into internal calculations
“hard-wired” cannot easily test other modeling choices
missing: models of CAD tools and optimizations (what is really “achievable”?)
missing: scope, comprehensive coverage
Shared, Worldwide Technology Extrapolation System : Flexibility
edit or define new parameters and relations between them
perform specific studies (but different studies at different times)
Quality
continuous improvements
world-wide participation of experts
Transparency
open-source mechanism
models visible to the user
No more redundant effort
permanent repository of first choice
adoptability and maintainability Shared, Worldwide Technology Extrapolation System
GTX: GSRC Technology Extrapolation System : GTX: GSRC Technology Extrapolation System GTX is set up as a framework for technology extrapolation
“Living Roadmap”
Open-source: http://vlsicad.cs.ucla.edu/GSRC/GTX/
2. CAD-IP Reuse : 2. CAD-IP Reuse How can we quickly develop the right design technology?
Problem: Currently takes 5-7 years to get a leading-edge algorithm into production tools
Result: Must solve today’s design problems with yesterday’s CAD technology
Problem: Published descriptions insufficient for replication or even comparison of algorithms
Result: Cannot identify, evaluate or advance the CAD technology leading edge
IF WE DO NOT KNOW WHERE THE LEADING EDGE OF CAD TECHNOLOGY IS, WE HAVE A REAL PROBLEM !!!
Unclear Leading Edge of CAD: A Real Problem : Unclear Leading Edge of CAD: A Real Problem Comparison of two LIFO-FM partitioner implementations
Min and Ave cut sizes from 100 single-start trials
Papers 1, 2 both published since mid-1998
This is a crisis !
2. CAD-IP Reuse : 2. CAD-IP Reuse How can we quickly develop the right design technology?
Problem: Currently takes 5-7 years to get a leading-edge algorithm into production tools
Result: Must solve today’s design problems with yesterday’s CAD technology
Problem: Published descriptions insufficient to enable replication or even comparison of algorithms
Result: Cannot identify, evaluate or advance the CAD technology leading edge
The TAT and QOR problems are not only for CAD customers, but for CAD itself !!!
productivity of CAD tool development (time-to-market)
quality of resulting CAD tools (quality-of-result)
Analogy: Hardware Design :: CAD Tool Design : Analogy: Hardware Design :: CAD Tool Design Hardware design is difficult
complex electrical engineering and optimization problems
mistakes are costly
verification and test not trivial
few can afford to truly exploit the limits of technology
A Winning Approach: Hardware IP reuse
CAD tools design is difficult
complex software engineering and optimization problems
mistakes can be showstoppers
verification and test not trivial
few can manage complexity of leading-edge approaches
A "Surprising Proposal”: CAD-IP reuse
What is CAD-IP? : What is CAD-IP? Data models and benchmarks
context descriptions and use models
testcases and good solutions
Algorithms and algorithm analyses
mathematical formulations
comparison and evaluation methodologies for algorithms
executables and source code of implementations
leading-edge performance results
Traditional (paper-based) publications
The Bookshelf: A Repository for CAD-IP : The Bookshelf: A Repository for CAD-IP “Community memory” for CAD-IP
data models
algorithms
implementations
Publication medium that enables efficient CAD R&D
benchmarks, performance results
algorithm descriptions and analyses
quality implementations (e.g., open-source UCLA PDTools)
Simplified comparisons to identify best approaches
Easier for industry to communicate new use models
http://vlsicad.cs.ucla.edu/GSRC/bookshelf
Proposed Change for Entire EDA Community : Proposed Change for Entire EDA Community Proposal: Data model and API are non-competitive and non-differentiating
Genesis, MilkyWay, CHDStd-IDM, UDM-Nike, … all very similar !
should be commoditized and shared by the community
“coopetition” distributes infrastructure burden, frees R&D resources
coopetition = cooperation + competition
Common data model across multiple vendors, users
common API is necessary; common database is not necessary
“control” issues solved by open-source model (www.openeda.org)
issues of integration and adoption costs still to be overcome
3. METRICS : 3. METRICS Did I really solve the problem?
Foundation of design optimization:
understanding of what should be optimized by which heuristic
understanding of design as a process
There are no standards or infrastructure for measuring and optimizing the semiconductor design process
“METRICS” = “measure, then improve”
design becomes less of an art and more of a formal discipline
Infrastructure
design process data collection infrastructure
data mining / visualization / diagnosis infrastructure
METRICS System Architecture : METRICS System Architecture
Benefits of METRICS : Benefits of METRICS Benefits for project management
accurate resource prediction at any point in design cycle
up front estimates for people, time, technology, EDA licenses, IP re-use...
accurate project post-mortems
everything tracked - tools, flows, users, notes
no “loose”, random data left at project end
management console
web-based, status-at-a-glance of tools, designs and systems at any point in project; correct go / no-go decisions as early as possible
Benefits for tool R&D
feedback on tool usage and parameters used
real benchmarking
Example Diagnoses : Example Diagnoses Placer runtime is linear in number of cells GOOD !
CPU_TIME = 12 + 0.027 NUM_CELLS (corr = 0.93)
Placer runtime becomes unpredictable at two particular utilization thresholds BAD !
80%, 95%
The Industry Needs METRICS Standards : The Industry Needs METRICS Standards Standard metrics naming across tools
same name « same meaning, independent of tool supplier
generic metrics and tool-specific metrics
no more ad hoc, incomparable log files
Standard schema for metrics database
Standard middleware for database interface
See: http://vlsicad.cs.ucla.edu/GSRC/METRICS
CAD Life Cycle Questions : CAD Life Cycle Questions What will the design problem look like?
answer: technology extrapolation
How can we quickly develop the right design technology?
answer: CAD-IP reuse
Did I really solve the problem?
Did the design process improve?
Did achievable design envelope get bigger?
answer: Metrics
Conclusions : Conclusions RTL-to-GDSII commoditizes existing SP&R market sectors
Design-manufacturing interface will change EDA
Design productivity gap threatens design quality
EDA industry must evolve and mature to achieve EDA industry productivity
Open, shared infrastructure can restore TAT, QOR of design technology
3 initiatives: Technology Extrapolation, CAD-IP Reuse, and METRICS
Outline : Outline Future DSM physical implementation technologies
design closure
design-manufacturing interface
Valuations
the significance of design productivity and design quality
structural aspects of the EDA industry
Values
toward maturity and a design productivity renaissance
Conclusions: Who Will Pay ?
“We Must Solve the CAD Productivity Challenges” : “We Must Solve the CAD Productivity Challenges” “Death Spiral” is a bad local optimum configuration
not enough value, not enough R&D, fragmentation of R&D
The design quality gap is just as dangerous as the design productivity gap
ASIC business model is at risk !
Solution lies in maturity of the EDA industry
“coopetitive” behavior of vendors and customers, together Happiness Future Today
“We Will Solve the CAD Productivity Challenges” : Build the non-differentiating, open-source EDA foundation
Bottom Up: data model (+API), concrete syntax (e.g., .lib + XML), tech extrapolation, silicon calibration/characterization, performance analyses, ...
EDPS, CHDStd, DAPIC experiences = useful foundation
world-wide cooperation needed (Japan/Asia, North America, Europe)
Understand that bottom-up commoditization of tools and adapters is inevitable
Bottom Up: Analyses first (RCX, DC, STA), then Syntheses (S, P & R)
pure tools $ static (?), but value remains in being best at leading edge
enormous resource savings in duplicated R&D, maintenance
more value from integrations, methodologies, faster technology delivery
Long-term: EDA moves upward in value chain
escapes “service” role
becomes more aware, specific to markets, manufacturing process “We Will Solve the CAD Productivity Challenges”
“Who Will Pay?” : “Who Will Pay?” Costs of cooperating are less than costs of not cooperating
Benefits of cooperation are immense
free up brains to improve Design Technology TAT and QOR
technology extrapolation + CAD-IP reuse + Metrics = delivery of solutions the right problems, at the right time, with measurable impact
We should welcome costs of openness, shared infrastructure
academia, vendor + internal EDA, designer communities together
It is a great future, if we make it happen !
Slide83 : THANK YOU !
Slide84 : EXTRA SLIDES
Synergies : Synergies CAD-IP
Reuse GTX Metrics Objective functions,
tool QOR metrics Estimates of
best-optimized
design, optimal
tradeoffs Models, measures
of algorithmic
activity Which problems
are critical?
What will
instances
look like? Optimized design
processes,
calibration data
for modeling
CAD
optimization Feasibility / sanity
checkers to embed
within a tool flow
GTX Engine : GTX Engine Contains no domain-specific knowledge
Evaluates rules in topological order
Performs studies
Multiple values through “sweeping”
Runs on three platforms (Solaris, Windows and Linux)
GTX Graphical User Interface (GUI) : GTX Graphical User Interface (GUI) Provides user interaction
Visualization (plotting, printing, saving to file)
4 views:
Parameters
Rules
Rule chain
Values in chain
The World of the Living Roadmap : The
Internet Sematech, GSRC
“The Golden Copy” The World of the Living Roadmap Technology
Models Richard Newton
Challenges for Applied Algorithmics : Research in mature areas can stall
incremental research - difficult and risky
implementations not available duplicated effort
too much trust which approach is really the best?
some results may not be replicable
‘not novel’ is common reason for paper rejection
exploratory research - paradoxically, lower-risk
novelty for the sake of novelty
yet, novel approaches must be well-substantiated
Pitfalls: questionable value, roadblocks, obsolete contexts
Challenges for Applied Algorithmics
“What Are Some Concrete, Industry-Wide Steps?” : “What Are Some Concrete, Industry-Wide Steps?” First step: open minds
Second step: agreements on scope of design activity
bound the interoperability problem by defining canonical design states, e.g.:
cycle-accurate microarchitecture
gate-level placement
global-routed but not detailed-routed
Third step: proofs that coopetition is feasible
how different or similar are (for example):
foundry process/rule description formats? library model generators?
IDM/CHDStd, UDM, Genesis, MilkyWay, ...?
AWE, ramp-Elmore, etc. interconnect delay calculations?
Where is the Solution ? (DAC-2000 Panel) : Where is the Solution ? (DAC-2000 Panel) A: RTL estimation
B: RTL synthesis + optimization
C: gate-level estimation
D: gate-level logic optimization
E: cell + wire sizing + physical support (e.g., P&R)
F: block placement, floorplanning + wireplanning + budgeting
G: gate-level place and route
H: other
Perfect Rectilinear Floorplanning : Perfect Rectilinear Floorplanning Fixed-die planning: find a coarse global floorplan, then migrate whitespace « overlap such that both disappear
Slide93 : See, for example: http://vlsicad.cs.ucla.edu/SLIP2000/ Kn Mn
What Does Process Variability Imply for EDA ? : What Does Process Variability Imply for EDA ? VERY DIFFICULT PROBLEMS !
We require much deeper understanding of process
coma effects (lens aberration)
halation (iso-dense effects on etch dynamics)
statistical variation in ion implant
Performance verification infrastructure may change
E.g., “delay” is no longer a number – it is a distribution
Must have complete, integrated, front-to-back solutions
All three examples: OPC, PSM, Area Fill
Long-term: must drive process requirements from system architecture and design technology roadmaps
RC and RLC Interconnect Delay Models : Five different interconnect models
Bakoglu’s model (RC)
[Alpert, Devgan and Kashyap, ISPD 2000] (RC)
[Ismail, Friedman and Neves, TCAD 19(1), 2000] (RLC)
[Kahng and Muddu, TCAD 1997] (RLC)
Extension of [Alpert, Devgan and Kashyap, ISPD 2000] (RLC) RC and RLC Interconnect Delay Models
Generic and Specific Tool Metrics : Generic and Specific Tool Metrics Partial list of metrics now being collected in Oracle8i
Example Testbed: Cadence SLC Flow : Example Testbed: Cadence SLC Flow DEF Placed DEF M
E
T
R
I
C
S Incr. Routed DEF Optimized DEF LEF
GCF,TLF Clocked DEF Constraints
Current Status of METRICS Initiative : Current Status of METRICS Initiative Current status
complete prototype of METRICS system with Oracle8i, Java Servlet, XML parser, and transmittal API library in C++
METRICS wrapper for Cadence and Cadence-UCLA flows, front-end tools (Ambit BuildGates and NCSim)
easiest proof of value: via use of regression suites
Issues for METRICS constituencies to solve
security: proprietary and confidential information
standardization: flow, terminology, data management, etc.
social: “big brother”, collection of social metrics, etc.
Ongoing work with EDA, designer communities to identify tool metrics of interest
users: metrics needed for design process insight, optimization
vendors: implementation of the metrics requested, with standardized naming / semantics
GTX Current Status : GTX Current Status Models implemented
cycle-time models of SUSPENS (with extension by Takahashi), BACPAC (Sylvester, Berkeley), Fisher (ITRS)
currently adding
GENESYS (with help from Georgia Inst. Tech.)
RIPE (with help from Rensselaer Univ.)
new device and power modules (Synopsys / Berkeley)
new SOI device model (Synopsys / Berkeley)
inductance models (Silicon Graphics / Berkeley / Synopsys)
yield and die cost models (CMU)
Studies performed in GTX
model and parameter sensitivity analyses
design optimization studies
Seeking contributions, suggestions of new models, studies