zen univ feb 2004

Flex-Cell Optimization: 

Flex-Cell Optimization A Paradigm Shift in High-Performance Cell-Based Design

The Power-User Dilemma: 

The Power-User Dilemma Custom Team=400 3 GHz, 3 Years Flex-Cell Opt Team=10 520 MHz 6 Months FPGA Cost / TTM Speed, Power, Area Takes too long! Results aren’t good enough!

The Timing Dilemma: 

The Timing Dilemma Design Team clock target – 350 MHz On Post-logic synth./Post-placement STA Only 300 MHz – Problem!! Options Design change Rewrite RTL – Tapeout Delay!! Better technology Smaller geometry – Tapeout delay and NRE cost!! Low-k technology – Yield hit!! Better tools Flex-Cell Optimization Custom-design benefits in std cell flow

Root of the Problem: 

Root of the Problem Various past studies, including a special session at DAC 2000 Std-Cell based design “an order of magnitude” lower performance than custom, at same process node Architecture Fixed cell library Layout Fixed cell library can account for as much as 25% of the performance shortfall

Rich vs Smart: 

Rich vs Smart Simply creating a “richer” cell library does not solve problem Too many cells hinder automated optimization Missing design-specific context information Well-known matching problems for larger cells Custom-crafted cells, for specific design, can inject large timing gains late in the design cycle Compute-intensive process Transistor netlist optimization Cell layout creation View generation

Flex-Cell Optimization -- Concept: 

Flex-Cell Optimization -- Concept

Prior Work: 

Prior Work Manual custom-crafting of cells, is well established Tactical cells: every high-performance design project uses some Automated transistor-level netlist creation/optimization Fishburn, Dunlop(1985): TILOS, transistor sizing Gavrilov et al (1997): Library-less synthesis Kanecko, Tian (1998): Concurrent cell generation and mapping of digital logic Liu, Abraham (1999): Transistor-level synthesis of combinational logic

Flex-Cell Optimization Targets : 

Flex-Cell Optimization Targets Eliminate deficiency due to fixed cell library Boost performance by 15% - 25% Close aggressive timing in days Retain proven existing cell-based design flow Use high-yield process, still get performance Minimal increase in die-size or power Get custom-design performance from std-cell-based flow

Key Steps : 

STA Cluster formation Critical Paths Key Steps Flex-cell (custom crafted) creation Gate-level optimization 1 Cell 13 Transistors 6 Wires Post synthesis netlist d

Flex-Cell Optimization with Physicals: 

Flex-Cell Optimization with Physicals Physically-aware STA Placement aware Congestion Blockage Multiple levels of accuracy for route info Steiner estimates Global route Detailed route** Physically-driven optimization Physically-aware clustering and mapping Physically-aware gate-level optimizations Low disturbance to existing placement Incremental legalization of placement Incremental re-computation of routes/estimates

Sample Flex-Cell: 

Sample Flex-Cell

Transistor-Level Optimization: 

Transistor-Level Optimization

Key Issues: 

Key Issues Judicious mix of gate-level and transistor-level optimization Judicious mix of discrete and continuous transistor sizing Effective use of transistor-level restructuring Fast and accurate transistor-level simulation 50x to 100x faster than Spice Accurate estimation of parasitics given transistor-level netlist

Impact On a Sample Critical Path : 

Impact On a Sample Critical Path 21% Improvement

Results (ZenTime): 

Results (ZenTime) 38K+ instance design 16% performance boost 297 MHz --> 344 MHz Implemented in a 0.13u process Added 132 flex-cells, 5,927 instances Without increasing power or area

Impact on Global Timing: 

Impact on Global Timing Initial frequency: 297 MHz Final frequency: 344 MHz

Timing Optimization Results: 

Timing Optimization Results with wire loads

I/O & Design Flow: 

I/O & Design Flow GDSII Back-end Design Front-end Design Constraints Design Library

Automated Flex-Cell Generation: 

Automated Flex-Cell Generation

Summary: 

Summary New dimension in optimization of cell-based designs Essential to find the “right balance” between gate-level and transistor-level optimization Better design quality, higher runtime Timing, Area, Power no longer a simple trade-off Possible to improve more than one, simultaneously Many challenges Lots of research opportunities!!

The History of Methodology Shifts: 

The History of Methodology Shifts