logging in or signing up System On Chip (SOC)-PPT CiTS Download Post to : URL : Related Presentations : Let's Connect Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Copy embed code: Embed: Flash iPad Dynamic Copy Does not support media & animations Automatically changes to Flash or non-Flash embed WordPress Embed Customize Embed URL: Copy Thumbnail: Copy The presentation is successfully added In Your Favorites. Views: 3303 Category: Entertainment License: All Rights Reserved Like it (1) Dislike it (0) Added: December 14, 2011 This Presentation is Public Favorites: 2 Presentation Description No description available. Comments Posting comment... By: shandilye (17 month(s) ago) how can i download it? Saving..... Post Reply Close Saving..... Edit Comment Close Premium member Presentation Transcript System On Chip - SoC: System On Chip - SoC Seminar by Rehnadas H S7 IT Roll no:54OVERVIEW: OVERVIEW Introduction . What is SoC ? Components of SoC . SoC architecture SoC cores. SoC interconnection. SoC design flow. SoC design considerations. Advantages & disadvantages . SoC Applications & future trends. Conclusion.INTRODUCTION: INTRODUCTION SOC technology is the ability to place multiple function “systems” on a single chip. Silicon chip along with the software running on it. SOC refers to integrating all components of a computer and other electronic s/ms into a single chip. Application is in the area of embedded systems. SOC is more cost effective than SiP since it increases the yield of fabrication & because its packaging is simpler. What is SoC ? SOC is integration of almost all components of a computer into a single integrated circuit. SOC consists of both h/w & s/w components that controls the microprocessor and peripherals. Components of SoC : Components of SoC HARDWARE SOFTWARE Processor such as ARM core. System bus-connecting the processor to other components- e.g. AMBA Bus. Memory-some types of ROM, EEPROM or Flash. Timers-oscillators, PLLs, real time clocks etc. LCD controllers or VGA Controller, with optional Touch Screen interface. External Interfaces for USB, Firewire , etc. & for flash memory- Compact Flash, SD Card, Memory Stick etc. Power management circuits, Interrupt Controller and Memory Interface. The operating system - ranges from a simple RTOS like eCOS or uITRON to high level OS such as Windows CE or Embedded Linux. The operating system layer, generally termed as the Board Support Package (BSP) abstracts the actual SoC HW. Device drivers - which control the peripherals. Middleware components - such as multimedia engines, protocol stacks etc. Application software - the UI, the media players, phone applications, browsers etc.SoC ARCHITECTURE: SoC A RCHITECTURE It consists of processor,system bus,timers,interrupt controller and power management circuits. SoC for multimedia platform requires large amount of audio & video processing. There are 2 schools of thoughts in the industry:Dedicated DSP & Dedicated multimedia blocks.PowerPoint Presentation: System on Chip cores One solution to the design productivity gap is to make ASIC designs more standardized by reusing segments of previously manufactured chips. These segments are known as “blocks”, “macros”, “cores” or “cells”. The blocks can either be developed in-house or licensed from an IP company. Cores are the basic building blocks . Soft Macro Reusable synthesizable RTL or netlist of generic library elements User of the core is responsible for the implementation and layout Firm Macro Structurally and topologically optimized for performance and area through floor planning and placement Exist as synthesized code or as a netlist of generic library elements Hard Macro Reusable blocks optimized for performance, power, size and mapped to a specific process technology Exist as fully placed and routed netlist and as a fixed layout such as in GDSII format .PowerPoint Presentation: System on Chip cores Reusability portability flexibility Predictability, performance, time to market Soft core Firm core Hard corePowerPoint Presentation: System on Chip cores Locating the required cores and associated contract discussions can be a lengthy process Identification of IP vendors Evaluation criteria Comparative evaluation exercise Choice of core Contract negotiations Reuse restrictions Costs: license, royalty, tool costs Core integration, simulation and verificationSolution is Design Re-use: Solution is Design Re-use Overcome complexity and verification issues by designing Intellectual Property (IP) to be re-usable . Done on such a scale that a new industry has been developed. Design activity is split into two groups: IP Authors – producers . IP Integrators – consumers . IP Authors produce fully verified IP libraries Thus making overall verification task more manageable IP Integrators select, evaluate, integrate IP from multiple vendors IP integrated onto Integration Platform designed with specific application in mindSystem on Chip interconnection: System on Chip interconnection Design reuse is facilitated if “standard” internal connection buses are used . All cores connect to the bus via a standard interface . Any-to-any connections easy but … Not all connections are necessary . Global clocking scheme . Power consumption . Standardization is being addressed by the Virtual Socket Interface Alliance (VSIA) For SoC interconnection,make use of the following buses for interconnection network: AMBA (Advanced Microcontroller Bus Architecture) is a collection of buses from ARM for satisfying a range of different criteria. APB (Advanced Peripheral Bus): simple strobed -access bus with minimal interface complexity. Suitable for hosting peripherals. ASB (Advanced System Bus): a multimaster synchronous system bus. AHB (Advanced High Performance Bus): a high- throughput synchronous system backbone. Burst transfers and split transactions.SoC DESIGN FLOW: SoC DESIGN FLOW Figure : System-on-a-Chip Design FlowPowerPoint Presentation: SoC DESIGN FLOW Top Level Design Unit Block Design Integration and Synthesis Trial Netlists System Level Verification Timing Convergence & Verification Fabrication DVT DVT Prep 4 14 5 4 Time in Weeks Time to Mask order 24 33 Unit Block Verification 4 2 With increasing Complexity of IC’s and decreasing Geometry, IC Vendor steps of Placement, Layout and Fabrication are unlikely to be greatly reduced In fact there is a greater risk that Timing Convergence steps will involve more iteration. Need to reduce time before Vendor Steps. Need to consider Layout issues up-front. SoC Design TimeSoC DESIGN CONSIDERATIONS: SoC DESIGN CONSIDERATIONS Process Technology Die size Power Hardware software partitioning Operating systemPowerPoint Presentation: ADVANTAGES & DISADVANTAGES There are several benefits in integrating a large digital system into a single integrated circuit . These include Lower cost per gate . Lower power consumption . Faster circuit operation . More reliable implementation . Smaller physical size . Greater design security . Easy-to-incorporate modern protocols & bluetooth to embedded systems. Porting PC s/w on embedded s/m. The principle drawbacks of SoC design are associated with the design pressures imposed on today’s engineers , such as : Time-to-market demands . Exponential fabrication cost . Increased system complexity . Increased verification requirements .MAJOR SOC APPLICATION & FUTURE TRENDS: MAJOR SOC APPLICATION & FUTURE TRENDS Speech Signal Processing . Image and Video Signal Processing . Information Technologies PC interface (USB, PCI,PCI-Express, IDE,..etc) Computer peripheries (printer control, LCD monitor controller, DVD controller,.etc) . Data Communication Wireline Communication: 10/100 Based-T, xDSL, Gigabit Ethernet,.. etc Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax, UWB, … ,etcCONCLUSION : CONCLUSION Technological advances mean that complete systems can now be implemented on a single chip . The benefits that this brings are significant in terms of speed , area and power . The drawbacks are that these systems are extremely complex requiring amounts of verification . The solution is to design and verify re-useable IP .THANK YOU: THANK YOU You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.