FEE dev IHEP

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Status of FEE development for RPCs in IHEP: 

Status of FEE development for RPCs in IHEP Alexander Kuznetsov Institute for High Energy Physics Protvino Moscow region, Russia

Content: 

Content 1. Requirements 2. Steps 3. Step1- discrete ICs for conditionong + FPGA 4. Plans

RO electronics: 

RO electronics General scheme for 64 channel read out Two parts: Conditioning (analog) FPGA (digital)

RO electronics: 

RO electronics Requirements - All FEE should be on board - One channel andlt; 1 cm2 - Anode PCB with pads should be multi layer PCB

RO electronics: 

RO electronics Steps for design and usage Approach for conditioning Preamp+comparator For 1 step - IC conditioning on pads within 1 cm2 - FPGA on side of anode PCB

RO electronics: 

RO electronics threshold andgt; 0.5 mV Preamp, 10x Comp, 5 mV Gate, 100 ns TTL pos signal for FPGA Was tested successfully in Dec02 beam run as separate board

RO electronics: 

RO electronics Step1 – analog part simulation

RO electronics: 

RO electronics Step1 – 6 layer PCB for 64 channels Layer meaning Anode pads Shield GND Signal CMOS lines Power layer Shield analog GND Component layer FPGA on the same PCB, out of RPC ALTERA EP1K50 All components (ICs) in SOT-23-5 packages

RO electronics: 

RO electronics Anode pad layer component layer Step1 – 6 layer PCB for 64 channels

RO electronics: 

RO electronics Step1 – 6 layer PCB for 64 channels One channel 1x1 cm2 Component layer

Plans: 

Plans Test first samples of the PCB which are ordered in March on real RPC

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