logging in or signing up mapld Candelora Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINTLite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 22 Category: Education License: All Rights Reserved Like it (0) Dislike it (0) Added: February 28, 2008 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Early output logic and Anti-Tokens: Early output logic and Anti-Tokens Charlie Brej APT Group Manchester UniversityOverview: Overview Synchronous Problems Asynchronous Logic Why? How? Solutions Early Output Anti-TokensProblems: Communication: Problems: Communication Communication horizon “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997] Clock distributed using wave pipelining Problems: Performance: Problems: Performance Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheadsClock! What is it good for?: Clock! What is it good for? No arguing with the clock 9am - 5pm. No excuses! Bundled-Data: Bundled-Data When you finish, do the next task Flexitime Request + Delay Acknowledge How do you know when you are finished?: How do you know when you are finished? Synchronous: Estimate Global timing reference Asynchronous (bundled-data) Estimate Local delay elements Asynchronous (delay-insensitive) When the data arrives IntrinsicBecoming Delay Insensitive: Becoming Delay Insensitive Dual-Rail Two wires 00 – NULL 01 – Zero 10 – One (11 – Not used) Four Phase handshake Return to zero R1 Ack R0 Early Output Logic: Early Output Logic Dual-Rail interfaces Output generated as early as possible Two Early output cases If either input is ‘0’ then the output is ‘0’ Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Early Output cases: Early Output casesValidity: Validity Unnecessary late inputs Must be acknowledged Must wait until they arrive Validity signal Latch generated Ready to be acknowledged Result before all inputs present Acknowledge after all inputs presentSynchronisation Hurts: Synchronisation Hurts No need to wait before generating result Need to wait for input in order to acknowledge it Unnecessary stallAnti-Tokens: Anti-Tokens Unnecessary late inputs Stall the entire stage Proactive approach Send a ‘cancel’ signal backward to the source Acknowledge before data arrives Anti-Token latches Assert validity earlyAnti-token generation: Anti-token generation 0 1 CAnti-token generation: Anti-token generation 0 A 1 CAnti-token Propagation: Anti-token Propagation 1 C AAnti-token Propagation: Anti-token Propagation 1 C A AAnti-token Token collisions: Anti-token Token collisions 1 1 A A 1 1 A A ? A ? 1Anti-token Token collisions: Anti-token Token collisions 1 1 A 1 1 A A 1 A 1 1 1 Remove Unnecessary computation: Remove Unnecessary computation Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheads Unnecessary Computation/DelaysSummary: Summary Asynchronous Delay Insensitive Safe No timing assumptions Average case performance Remove unnecessary computation Anti-tokens without mutual exclusion units You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
mapld Candelora Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINTLite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 22 Category: Education License: All Rights Reserved Like it (0) Dislike it (0) Added: February 28, 2008 This Presentation is Public Favorites: 0 Presentation Description No description available. Comments Posting comment... Premium member Presentation Transcript Early output logic and Anti-Tokens: Early output logic and Anti-Tokens Charlie Brej APT Group Manchester UniversityOverview: Overview Synchronous Problems Asynchronous Logic Why? How? Solutions Early Output Anti-TokensProblems: Communication: Problems: Communication Communication horizon “For a 60 nanometer process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997] Clock distributed using wave pipelining Problems: Performance: Problems: Performance Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheadsClock! What is it good for?: Clock! What is it good for? No arguing with the clock 9am - 5pm. No excuses! Bundled-Data: Bundled-Data When you finish, do the next task Flexitime Request + Delay Acknowledge How do you know when you are finished?: How do you know when you are finished? Synchronous: Estimate Global timing reference Asynchronous (bundled-data) Estimate Local delay elements Asynchronous (delay-insensitive) When the data arrives IntrinsicBecoming Delay Insensitive: Becoming Delay Insensitive Dual-Rail Two wires 00 – NULL 01 – Zero 10 – One (11 – Not used) Four Phase handshake Return to zero R1 Ack R0 Early Output Logic: Early Output Logic Dual-Rail interfaces Output generated as early as possible Two Early output cases If either input is ‘0’ then the output is ‘0’ Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Bit level pipelining: Bit level pipelining Forward completed parts of the result Pace work Don’t stall parts unless you have to Early Output cases: Early Output casesValidity: Validity Unnecessary late inputs Must be acknowledged Must wait until they arrive Validity signal Latch generated Ready to be acknowledged Result before all inputs present Acknowledge after all inputs presentSynchronisation Hurts: Synchronisation Hurts No need to wait before generating result Need to wait for input in order to acknowledge it Unnecessary stallAnti-Tokens: Anti-Tokens Unnecessary late inputs Stall the entire stage Proactive approach Send a ‘cancel’ signal backward to the source Acknowledge before data arrives Anti-Token latches Assert validity earlyAnti-token generation: Anti-token generation 0 1 CAnti-token generation: Anti-token generation 0 A 1 CAnti-token Propagation: Anti-token Propagation 1 C AAnti-token Propagation: Anti-token Propagation 1 C A AAnti-token Token collisions: Anti-token Token collisions 1 1 A A 1 1 A A ? A ? 1Anti-token Token collisions: Anti-token Token collisions 1 1 A 1 1 A A 1 A 1 1 1 Remove Unnecessary computation: Remove Unnecessary computation Cycle time Unbalanced Stages Clock Skew/Jitter Transistor Variability Signal Integrity Worst – Average case performance Real Computation Clock overheads Timing Assumption overheads Unnecessary Computation/DelaysSummary: Summary Asynchronous Delay Insensitive Safe No timing assumptions Average case performance Remove unnecessary computation Anti-tokens without mutual exclusion units