rfic 06 theo slides

Slide1: 

RMO4C-2 A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz Theo Chalvatzis and Sorin P. Voinigescu The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto, Canada

Outline: 

Outline Motivation ADC system level architecture Circuit design Measurements Conclusion

Motivation: 

Motivation Direct sampling receiver for 2-GHz CDMA basestation Transistor fT of 150..250 GHz and low-BVCEO naturally point to 1-bit ΔΣ digitization of RF signal Continuous-Time Bandpass ΔΣ topology offers: Higher resolution and lower power than other ADC types Low complexity (simple layout is important at 40 GHz!) LNA as input stage

System Level Architecture: 

System Level Architecture 2-GHz Gm-LC BPF 1-bit quantizer as DFF RZ pulse DACs Loop design in s-domain DAC(s) the TF of RZ DAC LNA & BPF1 BPF2

New Loop Filter Topology: 

New Loop Filter Topology MOS-HBT cascode provides: Linearity and low-noise with no degeneration Lower power supply (VGS<VBE) Bias at peak-gm current density for maximum linearity LE for input 50Ω matching: LEE for common mode rejection

New RZ DAC Topology: 

New RZ DAC Topology DAC with RZ pulse for immunity against loop delay Higher switching speed due to MOS-HBT cascode High gm/ITAIL ratio (due to HBT)

New 40-GHz Quantizer Topology: 

New 40-GHz Quantizer Topology MOS-HBT MSM flip-flop: 3 latches to compensate for metastability MOS on clock path to improve speed with low supply HBT on data path for high gain Min swing at quantizer input: 10mVpp 3 stages needed for full logic swing (300mVpp) at DAC input

40-GHz Bandwidth Clock Distribution: 

40-GHz Bandwidth Clock Distribution External clock distributed to 3 latches and 2 DACs EF-MOS-HBT cascode for increased bandwidth and large capacitive load drive

Slide9: 

Fabrication and Characterization of loop filter breakout and ADC

ADC Die Photograph: 

ADC Die Photograph 1.52x1.58mm2 ADC and filter breakout fabricated in STM’s 0.13μm SiGe BiCMOS: HBT fT/fmax=150/160 GHz 2μm finger width n-MOSFET fT/fmax=80/90 GHz Total power dissipation 1.6W from 2.5V

Loop Filter – Measurements: 

Loop Filter – Measurements Linearity and noise measured on a filter test structure Optimum bias point for maximum linearity: 0.4mA/μm

ADC – S-parameters: 

ADC – S-parameters Single-ended measurements Q=17 and BW3dB=120MHz ADC stable up to 65GHz S22<-7dB up to 65GHz and <-15dB up to 22GHz

ADC – Spectrum Measurements: 

ADC – Spectrum Measurements No idle tones present in-band Inset shows > 35dB/dec noise shaping Single-tone at 2-GHz ON Single-tone at 2-GHz OFF

ADC – SNDR Measurements: 

ADC – SNDR Measurements SNDR measured with Spectrum Analyzer Resolution BW lowered until noise floor remained constant (RBW < 50 KHz) Measurements taken for bandwidths between 1 MHz and 120 MHz

ADC – SNDR vs BW Measurements: 

ADC – SNDR vs BW Measurements SNDR=55dB over 60 MHz SNDR=52dB over 120 MHz

ADC – SFDR Two-Tone Measurements: 

ADC – SFDR Two-Tone Measurements Two-tone test with 2 GHz RF inputs at 10 MHz spacing PIN= -30dBm SFDR=61dB

ADC – 40-Gb/s Eye Diagram Jitter Measurements: 

ADC – 40-Gb/s Eye Diagram Jitter Measurements 2-GHz input sinusoid Feedback turned-off JitterRMS=375fs Jitter does not affect ADC resolution

ADC Performance: 

ADC Performance Figure of Merit (FOM) definition (lower better):

Conclusion: 

Conclusion First mm-wave sampling ΔΣ ADC in any technology (> 2xFs) Direct RF A/D Conversion at 2-GHz with 9-bit resolution over 60 MHz 11 bits over 60 MHz possible in this topology with: Improved filter linearity Higher filter Q Best FOM among all ADCs with clocks > 1 GHz 40-48 GS/s design scalable to 3.5/5/12 GHz

Acknowledgements: 

Acknowledgements Eric Gagnon and Morris Repeta for system performance specifications Nortel Networks for funding support STMicroelectronics for chip fabrication ECTI for lab access CMC for CAD tools