Lecture 15

© C Nyssen/Aberdeen College 2004All images © C Nyssen/Aberdeen College except where statedHP 830e Pocket PC © Hewlett Packard, with permissionAtari Jaguar ©2004 AtariAge, with permissionPrepared 21/01/04: 

D75P 34 – HNC Computer Architecture Lecture 15 RISC Program Analysis and Processor Comparisons. © C Nyssen/Aberdeen College 2004 All images © C Nyssen/Aberdeen College except where stated HP 830e Pocket PC © Hewlett Packard, with permission Atari Jaguar ©2004 AtariAge, with permission Prepared 21/01/04

Slide2: 

The program was written for a CISC (Complex) Instruction set. The time to execute each instruction varied, depending on how complex the instruction was. Today we will analyse the same program, but this time it has been specifically written for a RISC (Reduced Instruction Set) processor. Last time we saw how any computer program could be split into three separate “stages”, and we were given an assembly code program to analyse.

Slide3: 

There has been great debate in recent years as to the respective merits of each architecture. You can read about this for yourself in Workbook 3. This HP 820e handheld PC uses a 190 MHz 32-bit StrongArm, with a specially-written RISC version of Windows CE.

Slide4: 

Because the instructions are simpler, the RISC program needs more of them to accomplish the same thing. For this reason, RISC assembly programs are usually much longer than their CISC equivalents.

Slide5: 

No matter what the RISC instruction is, they all take exactly the same time to execute - usually 1 or 2 t-cycles, depending on the processor model. But because RISC instructions are quicker to execute, RISC processors are usually built to run at much lower frequencies. This Acorn is based on a 600MHz StrongArm. The Operating System is RISC OS 3.7. These machines are still in great demand by C and C++ developers.

Slide6: 

Again, you can write it next to the source code like this -

Slide7: 

Split the program into the three sections, using any unconditional jumps as a clue to where the loop might be.

Slide8: 

Everything in the red box will happen in the context of one complete loop. This also shows us what happens once only before and after the loop.

Slide9: 

We can now begin to calculate the total number of t-cycles required using the following formula (same as last week) –

Slide10: 

This time the jumps are easier to count, because we don’t have to worry about two values. Begin to fill in the formula -

Slide11: 

The only figure now missing is for how many complete loops are run. To establish this, we have to look at the data provided. We are told that the user inputs the following values each time the prompt is displayed – 6, o, %, f and s The stopping condition was defined on the line So again, the condition is met on the fifth pass of the loop.

Slide12: 

Remember that on the fifth pass, the loop is only the partial one, as the stopping condition is triggered halfway down. We therefore have four complete loops to count -

Slide13: 

You will now be asked to apply both RISC and CISC values to the given speeds of several processor. Start by working out the length of the t-cycle for each one -

Slide14: 

Now apply the t-cycle figures to each of the processor speeds. Remember that the RISC number goes with the RISC models and the CISC total with the CISC ones! You should now have a table showing the comparable times taken to execute the program on various speeds and models of processor. At it’s release in 1994, this Atari Jaguar was way ahead of it’s rivals, with it’s 64-bit RISC processor running at 26.59 MHz. Sadly, it couldn’t compete economically and production stopped in 1996.

Slide15: 

The next stage is to draw a graph to demonstrate these figures.

Slide16: 

This is where the scientific notation of numbers is useful - you can draw your graph based on fairly large numbers, applying a scientific notation to the axis! RISC Models CISC Models

Slide17: 

You will also be asked to provide an estimate of speed using your graph ... The answer is approximately 1.05 GHz.

Slide18: 

You will also have to state how much space in memory, each program will use. Complex instructions are different sizes. The more complicated the instruction, the more space it needs. Reduced instructions are always the same size - usually 32 bits, sometimes 64, depending on processor models. This Psion 5MX used a 36MHz ARM710T RISC CPU and ran EPOC as an operating system.

Slide19: 

You can write the sizes next to the instructions, like this….. And then just add them up! The CISC program uses 40 bytes …. … but the RISC one occupies 92!

Slide20: 

You don’t have to worry about the loop - because every time a jump is executed, it resets the program counter! So the MAR just “re-visits” the same areas of memory, over and over, until the stopping condition is met.

Slide21: 

Summary [1] To analyse any type of source code - establish how many t-cycles each instruction takes. establish what happens at the beginning, in the middle and at the end of the program. work out how many whole loops will be completed, and whether the last loop is a partial one. Work out how many t-cycles the RISC and the CISC versions will require to run. Fill in the table, keeping the results in scientific notation.

Slide22: 

Summary [2] Apply the total number of t-cycles to the processor speeds, to work out in real time, how long the source code will take to run. Keep all results in matching scientific notation, e.g. 0.50 x 10 –6 seconds. This makes it easier to depict on a graph, which will be used to estimate times for other theoretical models. Remember to work out how much memory space each program will require!