logging in or signing up Digital Signal Processing (DSP) Bhargav_1009 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 1610 Category: Education License: All Rights Reserved Like it (2) Dislike it (0) Added: April 25, 2010 This Presentation is Public Favorites: 3 Presentation Description No description available. Comments Posting comment... By: vikram13 (3 month(s) ago) plz willl u mail me its really uegent Saving..... Post Reply Close Saving..... Edit Comment Close By: marchana (10 month(s) ago) please mail this presentation to me on archana2.10.92@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close By: dattupragnu (13 month(s) ago) PLEASE CAN U MAIL DIS PRESENTATION 2 dattupragnu@Gmail.com plz sir Saving..... Post Reply Close Saving..... Edit Comment Close By: nkmj (15 month(s) ago) sir please mail this presentation to me on mishranisant59@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close By: anusha99 (15 month(s) ago) can u pls send dis ppt to my mail....anusha.allampilli@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close loading.... See all Premium member Presentation Transcript DSP Processors : DSP Processors Prepared By Makodia Bhargav [4010] (TMS320C54X) Guided By Mr. C.K.Vinchhi (Texas Instrument, Bangalore) Prof. S.B.Parmar (E&C Dept., SSEC) Shantilal Shah Engineering College, Bhavnagar. Content : Introduction Advantages of DSP over ASP Application General block diagram of DSP system Classification of DSPs DSP TMS320C54X Application Architecture Functional overview Comparison of ‘C54X with Micro-Processer Conclusion References Closer Content Introduction : What is DSP? D + S + P …!!! What is ASP? Why go Digital? Why do we need DSP processors? With DSP its east to.... Additionally DSP reduces.... Introduction Advantages of DSP over ASP : Component tolerance Component drift with time & temperature Noise Size of the system Storage of analog signal Flexibility Repeatability But…. DSP in “Real time operation..!!!” Advantages of DSP over ASP Application : Application Application (Cont…) : Some more noteworthy applications in different fields like:- Biomedical Military Instrumentation & Control General Purpose Application (Cont…) General block diagram of DSP system : General block diagram of DSP system External Memory Internal Memory Central Processing Unit Internal Buses PERIPHERALS Classification of DSP : Floating point DSPs Performs Integer operation. TMS320VC1X, C2X, C54X... Fixed Point DSPs Performs Integer & floating operation. TMS320VC3X, C4X, C67X... Classification of DSP TMS320C54X : Why ‘C54X? It’s a type of C5000TM low power DSP Efficiency Features Specific applications Cellular communication Stereo audio processing TMS320C54X TMS320C549 DSP device Nomenclature : TMS320C549 DSP device Nomenclature Architecture : classified as- Von Neumann Architecture Harvard Architecture Modified Harvard Architecture Architecture Von Neumann Architecture : Von Neumann Architecture Von Neumann (Cont…) : Von Neumann (Cont…) Inefficient for memory intensive operations One memory space Example: 20 Tap FIR4 4 Memory Accesses 1 Parallel MAC At least 80 cycles per output! Instructions and data have to be fetched in sequential order (known as the Von Neumann Bottleneck), limiting the operation bandwidth. Its design is simple Its mostly used for interfacing External devices. Next obvious step: Harvard Architecture : Next obvious step: Harvard Architecture Harvard Architecture (Cont…) : Uses physically separate memories for their instructions and data, requiring dedicated buses for each of them. Instructions and operands can therefore be fetched simultaneously. Different program and data bus widths are possible, allowing program and data memory to be better optimized to the architectural requirements. Ex.: If the instruction format requires 14 bits then program bus and memory can be made 14-bit wide, while the data bus and data memory remain 8-bit wide. Harvard Architecture (Cont…) Modified Harvard Architecture : Main difference over Harvard architecture is- Enable parallel memory access I/O controller May store coefficient in program memory (ROM) Modified Harvard Architecture I/O Controller ’C54X Functional block diagram : ’C54X Functional block diagram Functional Overview : CPU 40 bit ALU, two 40 bit accumulators Barrel shifter, CSSU 17 x17-bit multiplier/adder ALU Can performs two 16-bit operation simultaneously. Accumulators Guard bits Higher/Lower order words Barrel shifter Basically uses for a shift. Functional Overview Functional Overview (Cont…) : CSSU Compare, Select, & Store Unit Does it for accumulator’s lower & higher word. Status Register (ST0, ST1) Status of various modes & condition of the device. Temporary Register (TREG) Used for holding multiplicand for multiply and accumulate instruction. Functional Overview (Cont…) ‘C54X Buses and Pipelines : ‘C54X Buses and Pipelines Pipeline Issue : More inter-processer communication. Simpler processer hardware. Most ‘C54X code’s requires no special attention. Pipeline Issue Memory : The minimum memory address range is 192k words- 64k words in program, data and I/O space. On chip Memory option 24k of single access RAM (SARAM) 8k of dual access RAM (DARAM) 16k ROM Memory Security To prevent the on chip memory content from being extracted by a user. Memory Memory (Cont…) : Program & Data Memory 64k of 16-bit words Higher performance Lower cost & power 8M extended program memory Divided into 127 pages each of 32k words In addition to general purpose data memory CPU have reserved memory mapped register… Memory (Cont…) On Chip Peripherals : The on-chip peripheral options provided are: Software-programmable wait-state generator Programmable bank-switching Parallel I /O ports DMA controller Host-port interface (standard 8-bit, enhanced 8-bit, and 16-bit) Serial ports (standard, TDM, BSP, and McBSP) General-purpose I/O pins 16-bit timer with 4-bit prescaler Phase-locked loop (PLL) clock generator On Chip Peripherals Buffered Serial Port (BSP) : Superset of std serial port High speed data transfers Reduced interrupt latencies Read & Write to 2K words of RAM CPU not burdened Buffered Serial Port (BSP) Host Port Interface (HPI) : 8 bit parallel port Interfacing MCU Shared DARAM 2K word memory SAM Mode: DSP and MCU 64 MBps @ 40 MHz HOM mode: DSP and MCU 160 MBps @ 40 MHz IDLE2 Host Port Interface (HPI) Comparison of DSP with micro-processor : Instruction cycle Instruction execution Operand fetch from memory Memories ON/Chip- OFF/Chip memories Program flow control Queuing/Pipelining Address generation Address/Data bus multiplexing Computation unit ON Chip address and data buses Addressing modes Comparison of DSP with micro-processor Comparison on the basis of the following parameters: Conclusion : Foundation of Digital revolution. Optimization. Flexibility. Performance. Conclusion References : Books: Digital signal processing – N.G.Palan Digital signal processing– Shalivinaham Advance digital signal processing– Sherferd E-Books/ Links: www.ti.com www.google\dsp\.com www.howstuffworks.com www.en.wekipedia.com References Thank You : Thank You You do not have the permission to view this presentation. In order to view it, please contact the author of the presentation.
Digital Signal Processing (DSP) Bhargav_1009 Download Post to : URL : Related Presentations : Share Add to Flag Embed Email Send to Blogs and Networks Add to Channel Uploaded from authorPOINT lite Insert YouTube videos in PowerPont slides with aS Desktop Copy embed code: (To copy code, click on the text box) Embed: URL: Thumbnail: WordPress Embed Customize Embed The presentation is successfully added In Your Favorites. Views: 1610 Category: Education License: All Rights Reserved Like it (2) Dislike it (0) Added: April 25, 2010 This Presentation is Public Favorites: 3 Presentation Description No description available. Comments Posting comment... By: vikram13 (3 month(s) ago) plz willl u mail me its really uegent Saving..... Post Reply Close Saving..... Edit Comment Close By: marchana (10 month(s) ago) please mail this presentation to me on archana2.10.92@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close By: dattupragnu (13 month(s) ago) PLEASE CAN U MAIL DIS PRESENTATION 2 dattupragnu@Gmail.com plz sir Saving..... Post Reply Close Saving..... Edit Comment Close By: nkmj (15 month(s) ago) sir please mail this presentation to me on mishranisant59@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close By: anusha99 (15 month(s) ago) can u pls send dis ppt to my mail....anusha.allampilli@gmail.com Saving..... Post Reply Close Saving..... Edit Comment Close loading.... See all Premium member Presentation Transcript DSP Processors : DSP Processors Prepared By Makodia Bhargav [4010] (TMS320C54X) Guided By Mr. C.K.Vinchhi (Texas Instrument, Bangalore) Prof. S.B.Parmar (E&C Dept., SSEC) Shantilal Shah Engineering College, Bhavnagar. Content : Introduction Advantages of DSP over ASP Application General block diagram of DSP system Classification of DSPs DSP TMS320C54X Application Architecture Functional overview Comparison of ‘C54X with Micro-Processer Conclusion References Closer Content Introduction : What is DSP? D + S + P …!!! What is ASP? Why go Digital? Why do we need DSP processors? With DSP its east to.... Additionally DSP reduces.... Introduction Advantages of DSP over ASP : Component tolerance Component drift with time & temperature Noise Size of the system Storage of analog signal Flexibility Repeatability But…. DSP in “Real time operation..!!!” Advantages of DSP over ASP Application : Application Application (Cont…) : Some more noteworthy applications in different fields like:- Biomedical Military Instrumentation & Control General Purpose Application (Cont…) General block diagram of DSP system : General block diagram of DSP system External Memory Internal Memory Central Processing Unit Internal Buses PERIPHERALS Classification of DSP : Floating point DSPs Performs Integer operation. TMS320VC1X, C2X, C54X... Fixed Point DSPs Performs Integer & floating operation. TMS320VC3X, C4X, C67X... Classification of DSP TMS320C54X : Why ‘C54X? It’s a type of C5000TM low power DSP Efficiency Features Specific applications Cellular communication Stereo audio processing TMS320C54X TMS320C549 DSP device Nomenclature : TMS320C549 DSP device Nomenclature Architecture : classified as- Von Neumann Architecture Harvard Architecture Modified Harvard Architecture Architecture Von Neumann Architecture : Von Neumann Architecture Von Neumann (Cont…) : Von Neumann (Cont…) Inefficient for memory intensive operations One memory space Example: 20 Tap FIR4 4 Memory Accesses 1 Parallel MAC At least 80 cycles per output! Instructions and data have to be fetched in sequential order (known as the Von Neumann Bottleneck), limiting the operation bandwidth. Its design is simple Its mostly used for interfacing External devices. Next obvious step: Harvard Architecture : Next obvious step: Harvard Architecture Harvard Architecture (Cont…) : Uses physically separate memories for their instructions and data, requiring dedicated buses for each of them. Instructions and operands can therefore be fetched simultaneously. Different program and data bus widths are possible, allowing program and data memory to be better optimized to the architectural requirements. Ex.: If the instruction format requires 14 bits then program bus and memory can be made 14-bit wide, while the data bus and data memory remain 8-bit wide. Harvard Architecture (Cont…) Modified Harvard Architecture : Main difference over Harvard architecture is- Enable parallel memory access I/O controller May store coefficient in program memory (ROM) Modified Harvard Architecture I/O Controller ’C54X Functional block diagram : ’C54X Functional block diagram Functional Overview : CPU 40 bit ALU, two 40 bit accumulators Barrel shifter, CSSU 17 x17-bit multiplier/adder ALU Can performs two 16-bit operation simultaneously. Accumulators Guard bits Higher/Lower order words Barrel shifter Basically uses for a shift. Functional Overview Functional Overview (Cont…) : CSSU Compare, Select, & Store Unit Does it for accumulator’s lower & higher word. Status Register (ST0, ST1) Status of various modes & condition of the device. Temporary Register (TREG) Used for holding multiplicand for multiply and accumulate instruction. Functional Overview (Cont…) ‘C54X Buses and Pipelines : ‘C54X Buses and Pipelines Pipeline Issue : More inter-processer communication. Simpler processer hardware. Most ‘C54X code’s requires no special attention. Pipeline Issue Memory : The minimum memory address range is 192k words- 64k words in program, data and I/O space. On chip Memory option 24k of single access RAM (SARAM) 8k of dual access RAM (DARAM) 16k ROM Memory Security To prevent the on chip memory content from being extracted by a user. Memory Memory (Cont…) : Program & Data Memory 64k of 16-bit words Higher performance Lower cost & power 8M extended program memory Divided into 127 pages each of 32k words In addition to general purpose data memory CPU have reserved memory mapped register… Memory (Cont…) On Chip Peripherals : The on-chip peripheral options provided are: Software-programmable wait-state generator Programmable bank-switching Parallel I /O ports DMA controller Host-port interface (standard 8-bit, enhanced 8-bit, and 16-bit) Serial ports (standard, TDM, BSP, and McBSP) General-purpose I/O pins 16-bit timer with 4-bit prescaler Phase-locked loop (PLL) clock generator On Chip Peripherals Buffered Serial Port (BSP) : Superset of std serial port High speed data transfers Reduced interrupt latencies Read & Write to 2K words of RAM CPU not burdened Buffered Serial Port (BSP) Host Port Interface (HPI) : 8 bit parallel port Interfacing MCU Shared DARAM 2K word memory SAM Mode: DSP and MCU 64 MBps @ 40 MHz HOM mode: DSP and MCU 160 MBps @ 40 MHz IDLE2 Host Port Interface (HPI) Comparison of DSP with micro-processor : Instruction cycle Instruction execution Operand fetch from memory Memories ON/Chip- OFF/Chip memories Program flow control Queuing/Pipelining Address generation Address/Data bus multiplexing Computation unit ON Chip address and data buses Addressing modes Comparison of DSP with micro-processor Comparison on the basis of the following parameters: Conclusion : Foundation of Digital revolution. Optimization. Flexibility. Performance. Conclusion References : Books: Digital signal processing – N.G.Palan Digital signal processing– Shalivinaham Advance digital signal processing– Sherferd E-Books/ Links: www.ti.com www.google\dsp\.com www.howstuffworks.com www.en.wekipedia.com References Thank You : Thank You