A and D PCB Talk

Mixed Analog and Digital Circuit Boards for the ATLAS TRT : Mixed Analog and Digital Circuit Boards for the ATLAS TRT Nandor Dressnandt, Godwin Mayers, Toni Munar, Mitch Newcomer, Rick Van Berg, Brig Williams University of Pennsylvania Bjorn Lundberg Lund University Thurston Chandler, Colin Gay Yale Curt Baxter University of Indiana


TRT Physical Layout : TRT Physical Layout


Full Readout With Custom ASICS : Full Readout With Custom ASICS Low Level Differential Ternary Output (200uAStep) ASDBLRDTMROC LVDS (like) Clock/Control/Data Chip to Back End 16 Channel Readout ASIC Triplet


Barrel TRT Module End : Barrel TRT Module End HV Connector Arrays of 16 Straw Wire Anodes + 6 (AC coupled) Cathode Ref Barrel Support Frame Straw wire Density 30mm2/ straw 2X the density of Wheel


Stamp Board Approach : Stamp Board Approach Stamp FLEX Boards Kapton Connection Inputs from straw wires Output Roof Connector DTMROC in TQFP Chip on Board ASDBLR’s 16 Channel ASIC triplet Readout Cathode Reference Low Manufacturing Yield


ASIC Packaging : ASIC Packaging Custom Fine Pitch Ball Grid Arrays ASDBLR 8channel ASDBLR 8channel 16 Channel DTMROC 7.2 X 9.6mm 11X13mm


Stamp Board Threshold Scans : Stamp Board Threshold Scans Large Channel to Channel Variations due to Clock pickup # Hits in 75ns Gate Increasing Thresold


Signal Return Path : External currents added in signal return path can seriously corrupt straw signal. Signal Return Path ASD Preamp  Agnd  Connector pins  Straw reference Plane  HV CAP  Straw Cathode Ideal Signal Return These currents may be redirected over a large area by adding a low impedance network of conductors at the end of the module.


Single Analog and Digital Board Approach : Single Analog and Digital Board Approach Module 1 Small Triangle (one of 16 Custom Barrel Designs) Data Cable Connector (Unstuffed) DTMROC ASICS Top Side Digital Under side Analog ASDBLR ASICS underside Straw Pin  Floating Contact (NAIS) Connector Input Protection Board(s) 16 Straw modularity 1 of 10 Boards Shown Power Access along All Edges to Analog GND Encloses Detector Ends


First try at A and D Board : First try at A and D Board Hopeful but not very good. Clock pickup between supplies. Poor access to board grounds at the top of the board. Line over line differential clock / control routing near inputs. Trial areas where different routing techniques were studied. It did provide an essential case study to justify effects of various design techniques that otherwise would be simple speculation. Motivates Common Sense Design Rules: Separate Analog and Digital Power Domains. Maximize distance between Digital and layers and Analog power layers (lower Capacitance between domains). A and D Grounds join at board edges with small resistance at many locations (Current Flow Control). Blind Vias for Analog inputs and Digital clock, data and control.


Second A and D Barrel Board : Second A and D Barrel Board 90% of channels work acceptably. 1 – 2 channels per location exhibit serious clock pickup noise. Cause  Blind vias from inputs poking through Board shield layers. Straw Input Side with first inner layer Loc #3


Problem Location (#3) : Problem Location (#3) Position 3 Active Roof for Module 2 50% Threshold in DAC Counts Beam Clock Syncronous Time Bin 3.1ns /Bin 75ns total Width 50% occupancy threshold by time 3.1ns bin


AR2FS Location #3Layer 14 Component Side : AR2FS Location #3 Layer 14 Component Side Input Connector ASDBLR ASDBLR


AR2FS Location #3Layers 14 and 12 (analog side) : AR2FS Location #3 Layers 14 and 12 (analog side) Input Connector ASDBLR ASDBLR Side by side input traces under connector layer 12


AR2FS Location #3Layers 12, 14, and 1(DTMROC side) : AR2FS Location #3 Layers 12, 14, and 1(DTMROC side)


AR2FS Location #3Layers 14, 12, and 1 Clock vias Highlighted : AR2FS Location #3 Layers 14, 12, and 1 Clock vias Highlighted


AR2FS Location #3Layers 14, 12, 1, and 4 Clock vias Highlighted : AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias Highlighted


AR2FS Location #3Layers 14, 12, 1, and 4 Clock vias, Line 11 Highlighted : AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias, Line 11 Highlighted Measured Clock Pickup Threshold 50% min-max 100 DAC Cnts Ch #7


AR2FS Location #3Layers 14, 12, 1, and 4 Clock vias, Lines 11, 14, and 15 Highlighted : AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias, Lines 11, 14, and 15 Highlighted Measured Clock Pickup Threshold 50% min-max 180 DAC cnts Ch #9


AR2FS Location #3Layers 14, 12, 1, and 4 Clock vias, Lines 11, 14, and 15 Highlighted : AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias, Lines 11, 14, and 15 Highlighted Line 5 Highlighted in Light Gray Measured Clock Pickup Threshold 50% min-max 35 DAC Cnts Ch #3


Board Injection CapacitanceAnalog Blind Via to Digital Clk Trace : Board Injection Capacitance Analog Blind Via to Digital Clk Trace End of via layer 6 to nearby trace layer 4  250um separation. Measured 'via to trace' clock Injection charge. Min-Max/2 = 35cnts ~ 1.5fC Clock edge amplitude ~ 150mV C = Qinj/ Vclock= 10fF


Improved AR Board Design : Improved AR Board Design Stackup Component Signal w Gndd Area fill - Gnda at edges Signal Vdd Gndd Signal - Gnda ring at board edge. Signal (desperation layer) no clocked signals Gnda ring at board edge. Empty Vee (-3V) Gnda ( Shields inputs from Digital side.) Vcc ( Open under inputs to reduce capacitance) Signal ( threshold test pulse etc.) Gnda Area fill with slots under inputs Input Signal with Gnda Area fill Gnda Analog Components, Signal, Gnda Area fill


Visualization of AR Board : Visualization of AR Board Power Curt Baxter IU Digital Domain Clk/ Control Vdd Gndd Gnda Vee Vcc Analog Signal


Active Roof Layout Side ViewSingle Site (visualization) : Active Roof Layout Side View Single Site (visualization) Input Shield


Present PerformanceOn Detector Threshold AR 1 Scans : Present Performance On Detector Threshold AR 1 Scans


Latest Board Test Results(AR1FL)300 KHz Rate Threshold by location and channel : Latest Board Test Results(AR1FL) 300 KHz Rate Threshold by location and channel We are Awaiting the Edge Plated and improved GNDA Version Target Threshold ~2fC


Summary of our Approach : Summary of our Approach Separate Analog and Digital Domains vertically. Merge Grounds but Control Current flow. Shield inputs with analog ground plane. Minimize capacitance of input traces to other internal board layers. Complete shield of end of detector with analog ground. Encourage Digital energy to radiate away from Analog side. Keep clock /control/data above Vdd. Use board thickness to reduce capacitive coupling between Analog and Digital power planes. Use low level differential clock/control/data for off chip communication. We should note that these boards present a challenge to the board mfgrs Used so far. Not impossible but both expensive and often late in arrival.


Estimating Required VddFilter Capacitance : Estimating Required Vdd Filter Capacitance Assume 40MHz Clocked devices on DTMROC must be filtered locally to at least 1mV using local capacitance. AR1FL Vdd current measurements clock 'on' 'off' Vdd Current 1.1A 0.89A Difference current by chip – 19.1mA


Determining Filter Capacitance : Determining Filter Capacitance


DTMROC Vdd filtering : DTMROC Vdd filtering Model of Clocking Current (mostly on DTMROC) 40 Mhz Bx ~ 200pF 'on Chip' Aggregate clocked Capacitance Vdd Gndd Assume 1.5ns Switching Peak current ~300mA


AR board Vdd filtering : AR board Vdd filtering Bigger Picture AR board DTMROC’s


Vdd (Layer 3) – Gndd (Layer 4) Scope Measurements : Vdd (Layer 3) – Gndd (Layer 4) Scope Measurements 2 - .2uF caps / DTMROC 6 - .2uF caps / DTMROC 7mV peak – Peak 2.3mV RMS 17mV peak – Peak 5mV RMS Via impedance limits Improvement here.