21 6 05 CMSwkTrigger

CSC Track-Finder News: 

CSC Track-Finder News Dan Holmes University of Florida ( )

talk contents:: 

talk contents: SP Production status still on schedule to finish TF crate by end 05 Slice test status currently making L1As on real muons but at slow rate Khristian Khotov’s test beam DDU vs SP daq validations mismatches <0.1 %

quick recap; the CSC Track-Finder: 

quick recap; the CSC Track-Finder SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP CCB SBS 620 Controller Sector Processor Clock & Control Board Muon Sorter From MPC (chamber 4) From MPC (chamber 3) From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ MS Interfaces: 180 optical links from 60 EMU peripheral crates (3 fibers/crate) 72 SCSI cables to/from DTTF crates Single crate system, in production now

..and the new SP in production:: 

..and the new SP in production: Optical Transceivers 15 x 1.6 Gbit/s Links Front FPGA TLK2501 Transceiver Phi Local LUT Eta Global LUT Phi Global LUT TF logic mezz card

SP production history.. up to last CMS week: 

SP production history.. up to last CMS week There exist 3xSP boards, they work, one is making L1As at SX5 right now. ‘SP04’ is new prototype SP board: Fully compatible with ‘SP02’ (SP02 firmware just updated) 256 Mbit Flash RAM to instantly load all LUTs on power-up QPLL daughterboard for stable to clock to optical links On-board 40 MHz xtal for DDU link LEDs to indicate received LCTs Board i.d. switches Two ‘Conquest’ SP04 prototypes made 18/2/05 (#1,#2) BGA soldering on new SP04 bad.

SP04 production status cf Darin’s AR talk today: 

Two ‘Conquest’ SP04 prototypes made 18/2/05 boards re-worked by different company; Mar-Apr 05 pass basic SP-self tests, ongoing. New company, “Pactron” chosen for SP04 production two new pre-production SP04 received 1/6/05 (#3, #4) One board passes all single board tests including optical loop-back and full SP functionality check, tests ongoing. Will perform chain test with MPC and MS before launching rest of production ..Lev (engineer returns to Florida yes..) Final production plans final 16-board production to start July.. boards ready for testing September SP self and MPC tests.. MS tests with fully loaded new backplane: 2 months @ RICE ...done by end/yr... (if all runs smoothly!) Fully validated TF crate by end of 2005 SP04 production status cf Darin’s AR talk today

addendum... SP/MS Mezzanine Card Status: 

addendum... SP/MS Mezzanine Card Status Contains Track-Finding algorithm Same mezzanine card is used for Muon Sorter The previous (2002) prototype was fully validated Production version of mezzanine card fully compatible with prototype Production is nearly complete Despite some initial problems with connector assembly, 14 new mezzanine cards have been fully validated (+5 old) 2 others show some discrepancies and are under investigation

addendum...: TF Chain Test Results: 

addendum...: TF Chain Test Results Full TF crate tests with SP emulator boards shows some problems with grounding Solution found and tested. New TF backplane should be available by end July New ground planes and new signal routing will be implemented on TF backplane (Florida)

recap: slice test aim:: 

..to integrate into magnet test with one full 60° trigger sector up to 36 chambers provided P/C electronics available! (otherwise 40° slice: 24 CSCs) Sector 5, overlap with DT sectors 10+11 we can both provide and accept a trigger recap: slice test aim:

Peripheral Crate: 

Peripheral Crate right now: 1 chamber hooked up, gas, HV. Sending a ghost for each real hit. LCT LCT LCT 3 optical fibers to SP

peripheral crate  Track Finder: 

peripheral crate  Track Finder patch panel 3 x optical fibres from MPC patch panel Track Finder Crate 2m 178m 2m

The CSC Track Finder : 

The CSC Track Finder SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP CCB SBS 620 Controller Sector Processor Clock & Control Board Muon Sorter ME 1 To DAQ (via DDU) MS Interfaces: 180 optical links from 60 EMU peripheral crates (3 fibers/crate) 1 peripheral crate, 3 fibers Single crate system, in green barracks now TTC input 40.08 MHz Clock ME 1 ME 2 ME 3 ME 4

What do we need for a trigger?: 

What do we need for a trigger? The SP will send a L1A iff it can make a track from the LCTs: at least 2 coincident LCTs with “valid pattern” and appropriate quality bits set from TMB, MPC need at least one LCT on link corresponding to stations 2 or 3 and one in any other station need to fit within eta/phi/quality cuts real problem: we can only read out what we can trigger on.. ..only trigger on good data, hard to debug bad... To be done asap: firmware alteration to relax SP core cuts (done 17/6/05!) not implemented yet are cosmic challenge specific firmware alterations to increase cosmic rate for >1 disks (later) currently running a one chamber trigger ..will expand to two soon, then we can really start playing with real track extrapolations.

Development of SP bootstrap:: 

Development of SP bootstrap: We are learning.. ie. cold board arrives at CERN, what procedures do we do just to get it up and running? basic SP setup procedures: set up controlling PC: SBS and CAEN controllers, XDAQ, SP software. SPTTC & system test: send L1As, watch CCBs in all crates flash. ..ensures that the L1As we send out are reaching everything they need to! SP self tests: code to test all intra board links, chip & firmware validation, test self injection of data into SPY FIFOs, optical loop-back tests. ..ensure the hard & firmware pass basic checks before we go near anyone else!

Slide15: 

Development of SP bootstrap: Talk to the MPC upstream of us: test link (errors?!) from MPC; are links connected and active? read out PRBS & injected data to SP SPY channel; stream data over links, read it back. time-in MPCSP link latency; read out injected data use it to work out delay MPCSP, set delay register, make sure we can see just 1bx alone! (latency ~70bx understood, from fiber lengths etc. we retro-calculated 69.. ..should now be able to apply calculation to any setup..!?)

Slide16: 

Development of SP bootstrap: Interact MPCSPTTC procedures: inject test data to MPC to give L1A on SP; known data format, passes SP cuts. L1A is generated (and propagates through system) lots of flashing LEDs. Spot real CSC LCTs & send out L1As to system. (ok so right now it is a pretty low rate!) ..now have the basic service we want to provide.. inject test data to MPC to give & get back L1A; time in latency for L1ATTCSP. Need this to be able to read data out of our DAQ FIFO. .. then compare with DDU data..

Plans for the Immediate Future:: 

Plans for the Immediate Future: ..we would like to: finish timing-in ALCT wt CLCTs and then TMBs wrt each other. finish timing-in both DMB/DDU path and SP/DAQ path provide a stable trigger service to the Cosmic Challenge continue with DDU-SP trigger & data comparisons test & refine our own bootstrap procedures.. learn how to calculate latencies from scratch by hand. develop similar bootstrap tests with MS downstream of us? talk to DTs ..bat 904 tests..? document everything!!

Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05: 

cf talk given by Khristian at EMU meeting Sat 18/6/05 last years’ test beam... ~30 runs @ order 2->12k events comparing data from DAQ/DDU and SP/DAQ FIFO Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05 DAQ Peripheral Crates VME gigabit Sector Processor comparison between these two sets of data chambers

Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05: 

data passes basic DQM cuts real work is in assigning bx to asynchronous data stream so we get same L1A. Have to MPC sorting code etc. into account. May data identical to ~99.5% level, errors due to bad data from one chamber. (missing in DDU data) June data, correct to 99.95% level. Bad chamber removed from analysis. ...errors now due to failure to find correct bx in asynchronous data stream. looks like when data really compared frame-for-frame there is an exact match, ie. the hardware is working.. further, separately the SP simulation code has been validated to 100% against data. (ie. understand SP data) this is ongoing work, will continue with slice test etc.. Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05

Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05: 

Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05 Peripherial Crate #1 Sector Processor Crate #3 ME1/1 (CSC5) ME1/2 (CSC8) ME2/2 (CSC4) ME3/2 (CSC9) DAQ Peripherial Crate #2 ME1/1 (CSC6) VME gigabit Added Oct, also MPCtransparent mode ! May: just used 1 P/C

Slide21: 

Khristian Kotov’s May, June & October Test Beam Comparisons cf EMU meeting 18/6/05 May runs (red) “June” ( blue ) data have only 0.03% mismatches in average. Events with mismatch have right data frames, but wrong BX assignment October runs, results not presented yet..